系统架构采用单片8K HEVC解码器，用于8K高级BS接收系统

2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI:10.23919/VLSIC.2017.8008487

M. Nakajima, Daisuke Murakami, Hironori Kubo, Takahide Baba, Y. Miki

{"title":"系统架构采用单片8K HEVC解码器，用于8K高级BS接收系统","authors":"M. Nakajima, Daisuke Murakami, Hironori Kubo, Takahide Baba, Y. Miki","doi":"10.23919/VLSIC.2017.8008487","DOIUrl":null,"url":null,"abstract":"To implement 8K Advanced BS receiver system, 8K HEVC decoder SoC is developed as key component. To solve the exceeded required memory bandwidth over physical memory bandwidth limitation issue for realizing 8K decoder, two types of multi-cast write back scheme, including reference data multi-cast write back and output data multi-cast write back, are introduced. 8K HEVC decoder chip is fabricated in 28nm CMOS technology and SIP packaged with eight DDR3 memories.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"127 3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"System architecture with single chip 8K HEVC decoder for 8K advanced BS receiver system\",\"authors\":\"M. Nakajima, Daisuke Murakami, Hironori Kubo, Takahide Baba, Y. Miki\",\"doi\":\"10.23919/VLSIC.2017.8008487\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To implement 8K Advanced BS receiver system, 8K HEVC decoder SoC is developed as key component. To solve the exceeded required memory bandwidth over physical memory bandwidth limitation issue for realizing 8K decoder, two types of multi-cast write back scheme, including reference data multi-cast write back and output data multi-cast write back, are introduced. 8K HEVC decoder chip is fabricated in 28nm CMOS technology and SIP packaged with eight DDR3 memories.\",\"PeriodicalId\":176340,\"journal\":{\"name\":\"2017 Symposium on VLSI Circuits\",\"volume\":\"127 3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2017.8008487\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008487","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

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摘要

为了实现8K高级BS接收系统，开发了8K HEVC解码器SoC作为关键部件。为了解决实现8K解码器所需要的内存带宽超过物理内存带宽限制的问题，介绍了两种多播回写方案，包括参考数据多播回写和输出数据多播回写。8K HEVC解码器芯片采用28nm CMOS技术，SIP封装8个DDR3存储器。

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System architecture with single chip 8K HEVC decoder for 8K advanced BS receiver system

To implement 8K Advanced BS receiver system, 8K HEVC decoder SoC is developed as key component. To solve the exceeded required memory bandwidth over physical memory bandwidth limitation issue for realizing 8K decoder, two types of multi-cast write back scheme, including reference data multi-cast write back and output data multi-cast write back, are introduced. 8K HEVC decoder chip is fabricated in 28nm CMOS technology and SIP packaged with eight DDR3 memories.

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2017 Symposium on VLSI Circuits

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