{"title":"基于sar辅助管路ADC的免校准2.3 mW 73.2 dB SNDR 15b 100 MS/s 4级全差分环放大器","authors":"Yong Lim, M. Flynn","doi":"10.23919/VLSIC.2017.8008562","DOIUrl":null,"url":null,"abstract":"A four-stage fully differential ring amplifier in 40 nm CMOS improves gain to over 90 dB without compromising speed. It is applied in a 15b, 100 MS/s calibration-free SAR-assisted pipeline ADC. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. The ADC achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in a SNDR based Schreier FoM of 176.6 dB.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"389 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"33","resultStr":"{\"title\":\"A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SAR-assisted pipeline ADC\",\"authors\":\"Yong Lim, M. Flynn\",\"doi\":\"10.23919/VLSIC.2017.8008562\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A four-stage fully differential ring amplifier in 40 nm CMOS improves gain to over 90 dB without compromising speed. It is applied in a 15b, 100 MS/s calibration-free SAR-assisted pipeline ADC. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. The ADC achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in a SNDR based Schreier FoM of 176.6 dB.\",\"PeriodicalId\":176340,\"journal\":{\"name\":\"2017 Symposium on VLSI Circuits\",\"volume\":\"389 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"33\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2017.8008562\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008562","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 33
摘要
40纳米CMOS的四级全差分环放大器在不影响速度的情况下将增益提高到90 dB以上。它应用于15b, 100 MS/s免校准sar辅助流水线ADC。此外，一种新的自动零噪声滤波方法在不消耗额外功率的情况下降低了噪声。该ADC在1.1 V电源下实现73.2 dB SNDR (11.9b)和90.4 dB SFDR。它消耗2.3 mW，导致基于SNDR的Schreier FoM为176.6 dB。
A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SAR-assisted pipeline ADC
A four-stage fully differential ring amplifier in 40 nm CMOS improves gain to over 90 dB without compromising speed. It is applied in a 15b, 100 MS/s calibration-free SAR-assisted pipeline ADC. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. The ADC achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in a SNDR based Schreier FoM of 176.6 dB.
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