A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications

S. Yin, Ouyang Peng, Shibin Tang, Fengbin Tu, Xiudong Li, Leibo Liu, Shaojun Wei
{"title":"A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications","authors":"S. Yin, Ouyang Peng, Shibin Tang, Fengbin Tu, Xiudong Li, Leibo Liu, Shaojun Wei","doi":"10.23919/VLSIC.2017.8008534","DOIUrl":null,"url":null,"abstract":"An energy-efficient hybrid neural network (NN) processor is implemented in a 65nm technology. It has two 16×16 reconfigurable heterogeneous processing elements (PEs)arrays. To accelerate a hybrid-NN, the PE array is designed to support on demand partitioning and reconfiguration for parallel processing different NNs. To improve energy efficiency, each PE supports bit-width adaptive computing to meet variant bit-width of different neural layers. Measurement results show that this processor achieves a peak 409.6GOPS running at 200MHz and at most 5.09TOPS/W energy efficiency. This processor outperforms the state-of-the-art up to 5.2X in energy efficiency.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"111 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"70","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008534","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 70

Abstract

An energy-efficient hybrid neural network (NN) processor is implemented in a 65nm technology. It has two 16×16 reconfigurable heterogeneous processing elements (PEs)arrays. To accelerate a hybrid-NN, the PE array is designed to support on demand partitioning and reconfiguration for parallel processing different NNs. To improve energy efficiency, each PE supports bit-width adaptive computing to meet variant bit-width of different neural layers. Measurement results show that this processor achieves a peak 409.6GOPS running at 200MHz and at most 5.09TOPS/W energy efficiency. This processor outperforms the state-of-the-art up to 5.2X in energy efficiency.
用于深度学习应用的1.06- 5.09 TOPS/W可重构混合神经网络处理器
采用65nm工艺实现了一种节能的混合神经网络(NN)处理器。它有两个16×16可重构异构处理元素(pe)数组。为了加速混合神经网络,PE阵列被设计成支持按需划分和重构以并行处理不同的神经网络。为了提高能量效率,每个PE支持位宽自适应计算,以满足不同神经层的不同位宽。测试结果表明,该处理器在200MHz工作时最高可达409.6GOPS,最高可达5.09TOPS/W。这款处理器的能效比目前最先进的处理器高出5.2倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信