A capacitively-degenerated 100dB linear 20–150MS/s dynamic amplifier

Abstract

This paper presents a new dynamic residue amplifier for pipelined ADCs. With an input of 100mVpp, diff and 4x gain, it achieves −100dB THD, the lowest ever reported in dynamic amplifiers. Compared to the state-of-the-art, it exhibits >25dB better linearity with >2x larger output swing and similar noise performance. The key to this is a new linearization technique based on capacitive-degeneration. Fabricated in a 28nm CMOS, the prototype amplifier dissipates 87μW at a clock speed of 43MS/s and maintains −100dB THD up to 150MS/s.