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2017 Symposium on VLSI Circuits最新文献

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A 55μW 93.1dB-DR 20kHz-BW single-bit CT ΔΣ modulator with negative R-assisted integrator achieving 178.7dB FoM in 65nm CMOS 55μW 93.1dB-DR 20kHz-BW单比特CT ΔΣ调制器，带负r辅助积分器，在65nm CMOS中实现178.7dB FoM
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008540
Moonhyung Jang, Sangwoo Lee, Youngcheol Chae
{"title":"A 55μW 93.1dB-DR 20kHz-BW single-bit CT ΔΣ modulator with negative R-assisted integrator achieving 178.7dB FoM in 65nm CMOS","authors":"Moonhyung Jang, Sangwoo Lee, Youngcheol Chae","doi":"10.23919/VLSIC.2017.8008540","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008540","url":null,"abstract":"This paper presents a 3rd order single-bit CT ΔΣ modulator with active-RC integrators using negative-R assistant at virtual ground, which mitigates opamp's requirements including the thermal noise and linearity leading to a drastic power-saving. Fabricated in a 65nm CMOS process, the modulator occupies area of 0.27mm2. It achieves 100.5dB SFDR and 93.1dB DR in 20kHz BW, while consuming only 55μW from a 1.2V supply. This results in Schreier FoM of 178.7dB and Walden FoM of 63.1fJ/step.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114157764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS 采用时钟偏差校准的16nm CMOS次谐波注入锁定耦合振荡器的4GHz时钟分布架构
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008457
Lan-chou Cho, F. Kuo, Ron Chen, Jack Liu, C. Jou, F. Hsueh, R. Staszewski
{"title":"A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS","authors":"Lan-chou Cho, F. Kuo, Ron Chen, Jack Liu, C. Jou, F. Hsueh, R. Staszewski","doi":"10.23919/VLSIC.2017.8008457","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008457","url":null,"abstract":"We propose a new approach to an on-chip clock distribution scheme. It is based on distributed multi-GHz LC-tank oscillators generating local clocks. The oscillators are mutually coupled to align their frequencies and are further subharmonically injection-locked to a much lower frequency reference to align their phases. The final phase calibration is via adjusting their self-resonant frequencies. We demonstrate the scheme with two 4GHz digitally controlled oscillators (DCO) separated by 650um on a 16nm CMOS die, mutually coupled via a differential transmission line and injection-locked to a 125MHz reference. The proposed architecture achieves a sub-ps calibrated skew with 87fs rms jitter while consuming 4.3mW, resulting in −258dB clock FOM (jitter2 × power).","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114214565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.8V, 37nW, 42ppm/°C sub-bandgap voltage reference with PSRR of −81dB and line sensitivity of 51ppm/V in 0.18um CMOS 一个0.8V, 37nW, 42ppm/°C, PSRR为−81dB，线路灵敏度为51ppm/V的0.18um CMOS子带隙基准电压
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008463
Myungjun Kim, Seonghwan Cho
{"title":"A 0.8V, 37nW, 42ppm/°C sub-bandgap voltage reference with PSRR of −81dB and line sensitivity of 51ppm/V in 0.18um CMOS","authors":"Myungjun Kim, Seonghwan Cho","doi":"10.23919/VLSIC.2017.8008463","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008463","url":null,"abstract":"This paper presents a low-power, high-PSRR sub-bandgap voltage reference that operates under 1V supply. In order to achieve low temperature coefficient (TC), a CTAT circuit with internal feedback and a two-transistor PTAT circuit are proposed. For improved line sensitivity (LS) and PSRR, a self supply-regulated feedback is employed. Implemented in 0.18μm CMOS, the proposed voltage reference achieves an average TC of 42ppm/°C, PSRR of −81dB and LS of 51ppm/V while consuming 37nW at 0.8V supply.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121880058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 40nm split gate embedded flash macro with flexible 2-in-1 architecture, code memory with 140MHz read speed and data memory with 1M cycles endurance 40nm分闸嵌入式闪存宏，具有灵活的二合一架构，140MHz读取速度的代码存储器和1M周期持久时间的数据存储器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008481
Hung-Chang Yu, Ku-Feng Lin, Y. Chih, Jonathan Chang
{"title":"A 40nm split gate embedded flash macro with flexible 2-in-1 architecture, code memory with 140MHz read speed and data memory with 1M cycles endurance","authors":"Hung-Chang Yu, Ku-Feng Lin, Y. Chih, Jonathan Chang","doi":"10.23919/VLSIC.2017.8008481","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008481","url":null,"abstract":"This paper presents a 40nm 9.5Mb embedded flash (eflash) macro which can be partitioned as code storage and data storage in a single macro with enhanced read margin by using two design schemes: temperature adaptive reference scheme and flexible array partitioned scheme. By way of these design features, code storage memory achieves 140MHz read speed at the junction temperature of 160°C and data storage memory achieves 1M cycles endurance.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125089693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 3.2ppm/°C second-order temperature compensated CMOS on-chip oscillator using voltage ratio adjusting technique 一种采用电压比调节技术的3.2ppm/°C二阶温度补偿CMOS片上振荡器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008455
Guoqiang Zhang, Kosuke Yayama, Akio Katsushima, T. Miki
{"title":"A 3.2ppm/°C second-order temperature compensated CMOS on-chip oscillator using voltage ratio adjusting technique","authors":"Guoqiang Zhang, Kosuke Yayama, Akio Katsushima, T. Miki","doi":"10.23919/VLSIC.2017.8008455","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008455","url":null,"abstract":"A CMOS on-chip oscillator (OCO) for local interconnection network (LIN) bus is presented. The temperature dependence of the output frequency is compensated by the voltage ratio adjusting (VRA) technique. The frequency variation with supply voltage is reduced by a voltage regulator with a wide input range of 1.8 V to 5.0 V. The frequency shift caused by package stress is minimized by resistor placement. Over a temperature range of −40°C to 150°C, the measured temperature coefficients of the output frequency are 3.2ppm/°C without the effect of the package stress and 14.2ppm/°C with that, respectively. The measured frequency variation with supply voltage is within ±0.015%.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126348520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A distance-immune low-power 4-Mbps inductively-coupled bidirectional data link 一种距离免疫低功耗4mbps电感耦合双向数据链路
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008548
A. Yousefi, Dihang Yang, A. Abidi, D. Markovic
{"title":"A distance-immune low-power 4-Mbps inductively-coupled bidirectional data link","authors":"A. Yousefi, Dihang Yang, A. Abidi, D. Markovic","doi":"10.23919/VLSIC.2017.8008548","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008548","url":null,"abstract":"A distance-immune inductively coupled link is based on a free-running oscillator tuned by coupled resonators. It can transfer data at up to 4 Mbps and 2 Mbps in half duplex with an LSK uplink and ASK downlink, respectively (at BER< 5 × 10−8). In uplink direction, the implanted unit consumes less than 0.1 pJ/bit while transmitting.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114391469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A hybrid power amplifier using 3-phase 3-level class-D with 200nH inductors and current balancing technique 采用200nH电感和电流平衡技术的3相3电平d类混合功率放大器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008460
Jun-Han Choi, G. Cho
{"title":"A hybrid power amplifier using 3-phase 3-level class-D with 200nH inductors and current balancing technique","authors":"Jun-Han Choi, G. Cho","doi":"10.23919/VLSIC.2017.8008460","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008460","url":null,"abstract":"A hybrid power amplifier (PAhybrid), combining class-D and class-AB amplifier is demonstrated. As a specific structure for class-D, 3-level and 3-phase (3P3L) techniques are applied to reduce the current ripple to 1/12th of that of standard 2-level class-D amplifier. At the same time, the effective switching frequency increases by 6 times. Compared to the previous works which use several uH inductors, this paper only uses 200nH inductors with comparable efficiency, showing 30% increase in the proposed figure-of-merit (FOM).","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116264607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 140 MHz 1 Mbit 2T1C gain-cell memory with 60-nm indium-gallium-zinc oxide transistor embedded into 65-nm CMOS logic process technology 140 MHz 1 Mbit 2T1C增益单元存储器，60纳米铟镓氧化锌晶体管嵌入65纳米CMOS逻辑工艺技术
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008466
T. Ishizu, S. Nagatsuka, Momoyo Yamaguchi, A. Isobe, Y. Ando, D. Matsubayashi, K. Kato, H. B. Yao, C. Shuai, H. Lin, J. Y. Wu, M. Fujita, S. Yamazaki
{"title":"A 140 MHz 1 Mbit 2T1C gain-cell memory with 60-nm indium-gallium-zinc oxide transistor embedded into 65-nm CMOS logic process technology","authors":"T. Ishizu, S. Nagatsuka, Momoyo Yamaguchi, A. Isobe, Y. Ando, D. Matsubayashi, K. Kato, H. B. Yao, C. Shuai, H. Lin, J. Y. Wu, M. Fujita, S. Yamazaki","doi":"10.23919/VLSIC.2017.8008466","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008466","url":null,"abstract":"An embedded 1 Mbit 2T1C gain-cell memory macro using indium-gallium-zinc oxide semiconductor FETs (OSFETs) with an extremely low off-state current of less than 1 zA (10−21 A) was fabricated. In the 2T1C gain cell, an OSFET for the write operation was stacked over a SiFET for the read operation. The 1 Mbit macro was fabricated using a combination of 60-nm OSFET and 65-nm CMOS processes. It achieves a 140 MHz operation and data retention of more than 1 h. Its static power in the standby state and active power are 31 μW and 64 μW/MHz, respectively. The macro with long-term data retention can reduce the static power by power gating. 2T1C OSFET-based embedded memory is applicable to devices requiring high performance as well as low power.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"33 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132150784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A multi-mode WPAN (Bluetooth, BLE, IEEE 802.15.4) SoC for low-power and IoT applications 多模WPAN(蓝牙，BLE, IEEE 802.15.4) SoC，适用于低功耗和物联网应用
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008554
A. Zolfaghari, M. E. Said, Michael Youssef, Gang Zhang, Tom Liu, Federico Cattivelli, Yannis Ioannis Syllaios, Faisal Khan, Fang Fang, Jun Wang, Kuang-Yu Li, F. H. Liao, Devin Shengyu Jin, Vincent Roussel, Dong-U Lee, Farooq Hameed
{"title":"A multi-mode WPAN (Bluetooth, BLE, IEEE 802.15.4) SoC for low-power and IoT applications","authors":"A. Zolfaghari, M. E. Said, Michael Youssef, Gang Zhang, Tom Liu, Federico Cattivelli, Yannis Ioannis Syllaios, Faisal Khan, Fang Fang, Jun Wang, Kuang-Yu Li, F. H. Liao, Devin Shengyu Jin, Vincent Roussel, Dong-U Lee, Farooq Hameed","doi":"10.23919/VLSIC.2017.8008554","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008554","url":null,"abstract":"A multi-mode WPAN transceiver implemented in an SoC is presented. Fabricated in 40-nm CMOS, the chip supports IEEE 802.15.4 and all modes of Bluetooth. Consuming 7.8 mW from a 1.2-V supply, the receiver has a sensitivity of −104, −98, −95/−94/−88 dBm in 802.15.4, BLE and Bluetooth BDR/EDR2/EDR3, respectively. The transmitter has a power consumption of 10 mW to deliver 0 dBm output in the constant envelope mode and 14.5 mW in BT EDR.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127379246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Inside Waymo's self-driving car: My favorite transistors Waymo自动驾驶汽车内部:我最喜欢的晶体管
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008500
Daniel L. Rosenband
{"title":"Inside Waymo's self-driving car: My favorite transistors","authors":"Daniel L. Rosenband","doi":"10.23919/VLSIC.2017.8008500","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008500","url":null,"abstract":"Waymo's self-driving cars contain a broad set of technologies that enable our cars to sense the vehicle surroundings, perceive and understand what is happening in the vehicle vicinity, and determine the safe and efficient actions that the vehicle should take. Many of these technologies are rooted in advanced semiconductor technologies, e.g. faster transistors that enable more compute or low noise designs that enable the faintest sensor signals to be perceived. This paper summarizes a few areas where semiconductor technologies have proven to be fundamentally enabling to self-driving capabilities. The paper also lays out some of the challenges facing advanced semiconductors in the automotive context, as well as some of the opportunities for future innovation.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122959811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
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