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2017 Symposium on VLSI Circuits最新文献

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A 4μW, ADPLL-based implantable amperometric biosensor in 65nm CMOS 一种4μW、基于adpll的65nm CMOS可植入安培生物传感器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008566
Abhinav Agarwal, Albert Gural, M. Monge, Dvin Adalian, Samson Chen, A. Scherer, A. Emami
{"title":"A 4μW, ADPLL-based implantable amperometric biosensor in 65nm CMOS","authors":"Abhinav Agarwal, Albert Gural, M. Monge, Dvin Adalian, Samson Chen, A. Scherer, A. Emami","doi":"10.23919/VLSIC.2017.8008566","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008566","url":null,"abstract":"This paper presents a fully implantable, wirelessly powered subcutaneous amperometric biosensor. We propose a novel ultra-low power all-digital phase-locked loop (ADPLL) based potentiostat architecture for electrochemical sensing. The system is wirelessly powered by near-field RF coupling of an on-chip antenna to an external coil at 915 MHz. Bi-directional wireless telemetry supports data transmission from the sensor to the external reader (uplink) via backscattering, and reconfiguration of the sensor chip over the RF downlink. The 1.2×1.2 mm2 prototype is fabricated in TSMC 65nm CMOS process. The potentiostat achieves a 100pA sensitivity over a full scale current range of 0–350nA. The total power consumption of the system is 4μW.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126188175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 510nW 12-bit 200kS/s SAR-assisted SAR ADC using a re-switching technique 使用重开关技术的510nW 12位200kS/s SAR辅助SAR ADC
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008493
Yao-Sheng Hu, Kai-Yue Lin, Hsin-Shu Chen
{"title":"A 510nW 12-bit 200kS/s SAR-assisted SAR ADC using a re-switching technique","authors":"Yao-Sheng Hu, Kai-Yue Lin, Hsin-Shu Chen","doi":"10.23919/VLSIC.2017.8008493","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008493","url":null,"abstract":"This paper presents a 510nW 12-bit 200kS/s SAR-assisted SAR ADC in 40nm CMOS at 0.7V supply. A re-switching technique is proposed to suppress DNL spikes so that the size of DAC capacitor array can be minimized to reduce switching energy. A set of 2-way charge pump is used to decrease settling time constant and to increase sampling linearity. The prototype ADC achieves the DNL/INL performance of 0.5/0.79 LSB. Its SNDR and SFDR at Nyquist rate are 69.1dB and 81.72dB, respectively. It results in an FoMs of 182dB and an FoMw of 1.1fJ/c.-s.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126719607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 31.2pJ/disparity· pixel stereo matching processor with stereo SRAM for mobile UI application 31.2pJ/视差·像素立体声匹配处理器，带有立体声SRAM，用于移动UI应用
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008464
Jinsu Lee, Dongjoo Shin, K. Lee, H. Yoo
{"title":"A 31.2pJ/disparity· pixel stereo matching processor with stereo SRAM for mobile UI application","authors":"Jinsu Lee, Dongjoo Shin, K. Lee, H. Yoo","doi":"10.23919/VLSIC.2017.8008464","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008464","url":null,"abstract":"An energy-efficient and high-speed stereo matching processor is proposed for smart mobile devices with proposed stereo SRAM (S-SRAM) and independent regional integral cost (IRIC). Cost generation unit (CGU) with the proposed S-SRAM reduces 63.2% of CGU power consumption. The proposed IRIC enables cost aggregation unit (CAU) to obtain 6.4× of speed and 12.3% of the power reduction of CAU with pipelined integral cost generator (PICG). The proposed stereo matching processor, implemented in 65nm CMOS process, achieves 82fps and 31.2pJ/disparity-pixel energy efficiency at 30fps. Its energy efficiency is improved by 77.6% compared to the state-of-the-art.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132525391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS 基于14nm CMOS的2.4 mw 25 mhz BW 300 ms /s无源噪声整形SAR ADC
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008491
Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Rong-Xing Chu, Chao-Hsin Lu
{"title":"A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS","authors":"Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Rong-Xing Chu, Chao-Hsin Lu","doi":"10.23919/VLSIC.2017.8008491","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008491","url":null,"abstract":"This paper presents a SAR ADC using passive noise shaping and noise quantizer techniques. A ping-pong residue switching enables noise shaping at high sampling rate. The prototype in 14 nm achieves 69-dB SNDR at 25-MHz BW and 300 MS/s. The FOMs and FOMw are 169 dB and 20.5 fJ/conv.-step, respectively. With noise shaping only, the SNDR is 66.2 dB at 33-MHz BW and 400 MS/s.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131999473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell 使用28nm SRAM 6T位单元的序列相关挑战响应PUF
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008504
Supreet Jeloka, Kaiyuan Yang, M. Orshansky, D. Sylvester, D. Blaauw
{"title":"A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell","authors":"Supreet Jeloka, Kaiyuan Yang, M. Orshansky, D. Sylvester, D. Blaauw","doi":"10.23919/VLSIC.2017.8008504","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008504","url":null,"abstract":"Conventionally, SRAM PUFs are only used for chip ID. The proposed sequence dependent PUF expands the challenge-response space of an SRAM PUF by an order of rows(sequence length-1), making it suitable for authentication. In addition, it has a sequence dependent non-linear behavior making it more immune to machine learning attacks. In 28nm, the 64×64 SRAM-based PUF has a bit area of 388F2 with energy ranging from 30fJ/bit–88fJ/bit at 0.6V. It also provides high throughput, from 2.2Gbps to 6.8Gbps at 0.9V.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124897192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
A 0.3V VDDmin 4+2T SRAM for searching and in-memory computing using 55nm DDC technology 采用55nm DDC技术的0.3V VDDmin 4+2T SRAM，用于搜索和内存计算
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008465
Qing Dong, Supreet Jeloka, Mehdi Saligane, Yejoong Kim, Masaru Kawaminami, A. Harada, S. Miyoshi, D. Blaauw, D. Sylvester
{"title":"A 0.3V VDDmin 4+2T SRAM for searching and in-memory computing using 55nm DDC technology","authors":"Qing Dong, Supreet Jeloka, Mehdi Saligane, Yejoong Kim, Masaru Kawaminami, A. Harada, S. Miyoshi, D. Blaauw, D. Sylvester","doi":"10.23919/VLSIC.2017.8008465","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008465","url":null,"abstract":"A 4+2T SRAM is proposed that offers searching and logic functions. The cell uses the N-well as the write wordline (WL) and eliminates the access transistors. Decoupled read paths enable reliable multi-word activation for in-memory Boolean logic functions. The SRAM can reconfigure to BCAM/TCAM for searching operations, with 0.13fJ/search/bit at 0.35V. Forty test chips in 55nm deeply depleted channel (DDC) technology achieve worst-case 0.3 V VDDmin.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132038727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Semiconductor platforms for ultra low power IoT solutions 超低功耗物联网解决方案的半导体平台
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIT.2017.7998143
T. Dry, T. Letavic
{"title":"Semiconductor platforms for ultra low power IoT solutions","authors":"T. Dry, T. Letavic","doi":"10.23919/VLSIT.2017.7998143","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998143","url":null,"abstract":"Intelligent connected sensor and actuator endpoint nodes enable the Internet-of-Things (IoT). A brief overview of endpoint node functional blocks and requirements for low-power consumption are discussed. VLSI technology enablers for IoT include Ultra low Power (ULP) and Ultra Low Leakage (ULL) semiconductor process platform extensions. ULP and ULL implementations for bulk silicon technologies are presented and compared to fully-depleted silicon-on-insulator (FDSOI) technology. FDSOI utilizes Back Bias (BB) to improve performance and achieve the lowest dynamic and static power, enabling cost-effective low-power IoT applications.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124176938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 5.12-GHz fractional-N frequency synthesizer with an LC-VCO-based MDLL 基于lc - vco的MDLL的5.12 ghz分数n频率合成器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008458
Dai-En Jhou, W. Chang, Tai-Cheng Lee
{"title":"A 5.12-GHz fractional-N frequency synthesizer with an LC-VCO-based MDLL","authors":"Dai-En Jhou, W. Chang, Tai-Cheng Lee","doi":"10.23919/VLSIC.2017.8008458","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008458","url":null,"abstract":"An LC-VCO-based MDLL is presented in a fractional-N frequency synthesizer to extend its frequency multiplication factor and performance. By employing the proposed MUXs in the LC-VCO, it increases the loop bandwidth (BW) from 3MHz to 15MHz (nearly 0.4fREF) as well as flicker noise suppression. Moreover, the re-quantized delta-sigma modulator (DSM) is combined with the prototype in order to reduce spurious tones and in-band noise, which come from the gain error of the digital-to-time converter (DTC). Fabricated in a 40 nm CMOS technology, the proposed MDLL with a large frequency multiplication factor of 128 exhibits an integrated jitter of 177fs (integer-N) and 326fs (fractional-N) with power consumption of 1.81mW and 2.38mW from a 0.9V supply at 5.12GHz respectively. The FoMj of the proposed MDLL can be as good as −252.5dB (integer-N) and −246dB (fractional-N) with a reference frequency of 40MHz.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123011857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 150-μW 3rd-order butterworth passive-switched-capacitor filter with 92 dB SFDR 150μ w三阶巴特沃斯无源开关电容滤波器，92 dB SFDR
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008462
Zeynep Lulec, D. Johns, A. Liscidini
{"title":"A 150-μW 3rd-order butterworth passive-switched-capacitor filter with 92 dB SFDR","authors":"Zeynep Lulec, D. Johns, A. Liscidini","doi":"10.23919/VLSIC.2017.8008462","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008462","url":null,"abstract":"For the first time, complex conjugate poles are integrated on silicon by using only switches and capacitors. A general design methodology is proposed to implement low-pass transfer functions with sharper frequency profile compared to the passive-switched-capacitor topologies present in the literature. Theory and simulation results are validated through the measurements of a 0.13μm prototype filter. The 3rd-order filter has a cut-off frequency of 540 kHz, an integrated input referred noise of 17μV and out-of-band IIP3 of 55dBm, while consuming 150μW in the phase clock generator.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114582974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 1452-% power extraction improvement energy harvesting circuit with simultaneous energy extraction from a piezoelectric transducer and a thermoelectric generator 一种同时从压电换能器和热电发电机中提取能量的1452%功率提取改进能量收集电路
2017 Symposium on VLSI Circuits Pub Date : 2017-06-05 DOI: 10.23919/VLSIC.2017.8008482
K. Yoon, Sung-Wan Hong, Jun-Suk Bang, Sang-Han Lee, Sung-Won Choi, G. Cho
{"title":"A 1452-% power extraction improvement energy harvesting circuit with simultaneous energy extraction from a piezoelectric transducer and a thermoelectric generator","authors":"K. Yoon, Sung-Wan Hong, Jun-Suk Bang, Sang-Han Lee, Sung-Won Choi, G. Cho","doi":"10.23919/VLSIC.2017.8008482","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008482","url":null,"abstract":"This paper presents a dual-source energy harvesting circuit that efficiently and simultaneously extracts the energy from a piezoelectric transducer (PZT) and a thermoelectric generator (TEG). The harvester operates in a dual-source pile-up mode (DPM) to efficiently extract the energy from both sources with an increment of the damping force, resulting in a 1452% improvement of power extraction even without a TEG, which is the best among the-state-of-the-art works. Also, the harvester operates in a boost converter mode (BCM) without an additional power switch, achieving 75 % conversion efficiency at 450 μW output power. With a single-shared inductor, a simple control scheme enables the harvester to operate in both DPM and BCM by a time-multiplexing method, consuming low quiescent current of 240 nA.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133759964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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