Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Rong-Xing Chu, Chao-Hsin Lu
{"title":"基于14nm CMOS的2.4 mw 25 mhz BW 300 ms /s无源噪声整形SAR ADC","authors":"Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Rong-Xing Chu, Chao-Hsin Lu","doi":"10.23919/VLSIC.2017.8008491","DOIUrl":null,"url":null,"abstract":"This paper presents a SAR ADC using passive noise shaping and noise quantizer techniques. A ping-pong residue switching enables noise shaping at high sampling rate. The prototype in 14 nm achieves 69-dB SNDR at 25-MHz BW and 300 MS/s. The FOMs and FOMw are 169 dB and 20.5 fJ/conv.-step, respectively. With noise shaping only, the SNDR is 66.2 dB at 33-MHz BW and 400 MS/s.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS\",\"authors\":\"Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Rong-Xing Chu, Chao-Hsin Lu\",\"doi\":\"10.23919/VLSIC.2017.8008491\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a SAR ADC using passive noise shaping and noise quantizer techniques. A ping-pong residue switching enables noise shaping at high sampling rate. The prototype in 14 nm achieves 69-dB SNDR at 25-MHz BW and 300 MS/s. The FOMs and FOMw are 169 dB and 20.5 fJ/conv.-step, respectively. With noise shaping only, the SNDR is 66.2 dB at 33-MHz BW and 400 MS/s.\",\"PeriodicalId\":176340,\"journal\":{\"name\":\"2017 Symposium on VLSI Circuits\",\"volume\":\"136 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2017.8008491\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008491","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.4-mW 25-MHz BW 300-MS/s passive noise shaping SAR ADC with noise quantizer technique in 14-nm CMOS
This paper presents a SAR ADC using passive noise shaping and noise quantizer techniques. A ping-pong residue switching enables noise shaping at high sampling rate. The prototype in 14 nm achieves 69-dB SNDR at 25-MHz BW and 300 MS/s. The FOMs and FOMw are 169 dB and 20.5 fJ/conv.-step, respectively. With noise shaping only, the SNDR is 66.2 dB at 33-MHz BW and 400 MS/s.