A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS

Lan-chou Cho, F. Kuo, Ron Chen, Jack Liu, C. Jou, F. Hsueh, R. Staszewski
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引用次数: 2

Abstract

We propose a new approach to an on-chip clock distribution scheme. It is based on distributed multi-GHz LC-tank oscillators generating local clocks. The oscillators are mutually coupled to align their frequencies and are further subharmonically injection-locked to a much lower frequency reference to align their phases. The final phase calibration is via adjusting their self-resonant frequencies. We demonstrate the scheme with two 4GHz digitally controlled oscillators (DCO) separated by 650um on a 16nm CMOS die, mutually coupled via a differential transmission line and injection-locked to a 125MHz reference. The proposed architecture achieves a sub-ps calibrated skew with 87fs rms jitter while consuming 4.3mW, resulting in −258dB clock FOM (jitter2 × power).
采用时钟偏差校准的16nm CMOS次谐波注入锁定耦合振荡器的4GHz时钟分布架构
我们提出了一种芯片上时钟分配方案的新方法。它是基于分布式多ghz LC-tank振荡器产生本地时钟。振荡器相互耦合以使它们的频率对齐,并且进一步被亚谐波注入锁定到一个低得多的参考频率以使它们的相位对齐。最后的相位校准是通过调整它们的自谐振频率。我们演示了该方案,两个4GHz数字控制振荡器(DCO)在16nm CMOS芯片上相隔650um,通过差分传输线相互耦合,注入锁定到125MHz参考。所提出的架构实现了一个sub-ps校准的倾斜和87fs rms的抖动,同时消耗4.3mW,导致−258dB时钟FOM (jitter2 ×功率)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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