Kota Ando, Kodai Ueyoshi, Kentaro Orimo, H. Yonekawa, Shimpei Sato, Hiroki Nakahara, M. Ikebe, T. Asai, Shinya Takamaeda-Yamazaki, T. Kuroda, M. Motomura
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BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS
A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented. It features a massively parallel in-memory processing architecture and stores varieties of binary/ternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip. The 0.6 W, 1.4 TOPS chip achieves performance and energy efficiency that is 10–102 and 102–104 times better than a CPU/GPU/FPGA.
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