Computational locking: Accelerating lock-times in all-digital PLLs

Abstract

We propose computational-lock, a technique for accelerating frequency and phase-acquisition in all-digital PLLs during cold-start and re-lock. A wide-dynamic range, high resolution TDC is also proposed to further support the technique. Resulting lock-time improvements are evaluated through 50,000 repeated measurements of 65nm CMOS test-chips. Mean lock-times of 16Trefcik and 12Trefcik for cold-start and relock respectively are observed. Computational-lock does not impact steady-state PLL power and performance.