{"title":"采用固有无源积分器和电容反馈的40nm CMOS 0.028mm2 19.8fJ/step二阶vco CT ΔΣ调制器","authors":"Shaolan Li, Nan Sun","doi":"10.23919/VLSIC.2017.8008538","DOIUrl":null,"url":null,"abstract":"This paper presents an OTA-less 2<sup>nd</sup>-order VCO-based CT ΔΣ modulator featuring a passive integrator that makes use of the VCO's inherent parasitic effect. A low-power capacitive feedback technique is also presented for robust loop compensation. Fabricated in 40nm CMOS, the prototype occupies 0.028mm<sup>2</sup> of active area and consumes 524μW when sampling at 330MHz. The ΔΣM achieved peak Walden FoM of 19.8fJ/step with 68.6dB SNDR over 6MHz BW.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 0.028mm2 19.8fJ/step 2nd-order VCO-based CT ΔΣ modulator using an inherent passive integrator and capacitive feedback in 40nm CMOS\",\"authors\":\"Shaolan Li, Nan Sun\",\"doi\":\"10.23919/VLSIC.2017.8008538\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an OTA-less 2<sup>nd</sup>-order VCO-based CT ΔΣ modulator featuring a passive integrator that makes use of the VCO's inherent parasitic effect. A low-power capacitive feedback technique is also presented for robust loop compensation. Fabricated in 40nm CMOS, the prototype occupies 0.028mm<sup>2</sup> of active area and consumes 524μW when sampling at 330MHz. The ΔΣM achieved peak Walden FoM of 19.8fJ/step with 68.6dB SNDR over 6MHz BW.\",\"PeriodicalId\":176340,\"journal\":{\"name\":\"2017 Symposium on VLSI Circuits\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2017.8008538\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008538","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.028mm2 19.8fJ/step 2nd-order VCO-based CT ΔΣ modulator using an inherent passive integrator and capacitive feedback in 40nm CMOS
This paper presents an OTA-less 2nd-order VCO-based CT ΔΣ modulator featuring a passive integrator that makes use of the VCO's inherent parasitic effect. A low-power capacitive feedback technique is also presented for robust loop compensation. Fabricated in 40nm CMOS, the prototype occupies 0.028mm2 of active area and consumes 524μW when sampling at 330MHz. The ΔΣM achieved peak Walden FoM of 19.8fJ/step with 68.6dB SNDR over 6MHz BW.