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2017 Symposium on VLSI Circuits最新文献

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A 1.7nW PLL-assisted current injected 32KHz crystal oscillator for IoT 用于物联网的1.7nW锁相环辅助电流注入32KHz晶体振荡器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008551
Yu Zeng, Taekwang Jang, Qing Dong, Mehdi Saligane, D. Sylvester, D. Blaauw
{"title":"A 1.7nW PLL-assisted current injected 32KHz crystal oscillator for IoT","authors":"Yu Zeng, Taekwang Jang, Qing Dong, Mehdi Saligane, D. Sylvester, D. Blaauw","doi":"10.23919/VLSIC.2017.8008551","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008551","url":null,"abstract":"This paper presents a PLL-assisted crystal oscillator using a current switching phase detector (PD) with intrinsic 90° phase offset for IoT applications. The PLL provides accurate pulse injection timing into the XO, sustaining its oscillation at only 100mV amplitude and ensuring robustness operation across PVT. This technique achieves high energy injection efficiency and avoids the use of power hungry amplifiers. Measured power is 1.7nW at room temperature and operation is demonstrated from −20–80°C and across 3 corner wafers.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131776507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET 基于164fsrms 9 ~ 18ghz采样鉴相器的锁相环，具有带内噪声抑制和16nm FinFET的鲁棒频率采集功能
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008474
M. Raj, Ade Bekele, D. Turker, P. Upadhyaya, Y. Frans, Ken Chang
{"title":"A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET","authors":"M. Raj, Ade Bekele, D. Turker, P. Upadhyaya, Y. Frans, Ken Chang","doi":"10.23919/VLSIC.2017.8008474","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008474","url":null,"abstract":"A sampling phase detector (SPD) based PLL is presented. The high gain of this programmable SPD suppresses PLL's in-band noise and controls its bandwidth. Instead of sampling the VCO output directly like sub-sampling PLLs, the output of the frequency divider is sampled. This improves capture range and eases high frequency design while maintaining in-band noise reduction. The design uses a single charge pump based frequency acquisition technique with programmability for robust operation. The PLL is realized in a 16nm FinFET process. The SPD improves the measured inband phase noise from −90.6dBc/Hz to −104.1dBc/Hz at 18GHz with RMS jitter of 164fs when integrated over 10KHz–100MHz, while consuming 29.2mW. 2X frequency range of 9-to-18GHz is demonstrated using two LC VCOs.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134623679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS 一种用于蓝牙LE的0.5V 1.6mW 2.4GHz分数n全数字锁相环，具有pvt不敏感的TDC，采用28nm CMOS开关电容倍频器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/vlsic.2017.8008472
F. Kuo, Seyednaser Pourmousavian, T. Siriburanon, Ron Chen, Lan-chou Cho, C. Jou, F. Hsueh, R. Staszewski
{"title":"A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS","authors":"F. Kuo, Seyednaser Pourmousavian, T. Siriburanon, Ron Chen, Lan-chou Cho, C. Jou, F. Hsueh, R. Staszewski","doi":"10.23919/vlsic.2017.8008472","DOIUrl":"https://doi.org/10.23919/vlsic.2017.8008472","url":null,"abstract":"This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of −106 dBc/Hz (FoM of −239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122078120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET 一种12b 61dB SNDR 300MS/s SAR ADC，具有基于逆变器的前置放大器和14nm CMOS FinFET共模调节DAC
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008506
D. Luu, L. Kull, T. Toifl, C. Menolfi, M. Braendli, P. Francese, T. Morf, M. Kossel, Hazar Yueksel, A. Cevrero, I. Ozkaya, Qiuting Huang
{"title":"A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET","authors":"D. Luu, L. Kull, T. Toifl, C. Menolfi, M. Braendli, P. Francese, T. Morf, M. Kossel, Hazar Yueksel, A. Cevrero, I. Ozkaya, Qiuting Huang","doi":"10.23919/VLSIC.2017.8008506","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008506","url":null,"abstract":"A 300MS/s 12b SAR ADC achieving 61.6dB peak SNDR is presented. It reaches 60.5dB SNDR and 78.7dB SFDR with 0.8Vpp,diff input amplitude at Nyquist. The key elements are a comparator with inverter-based preamplifier and a SAR-based common-mode regulation. The regulation adjusts the common mode on a sample-by-sample basis to improve common-mode rejection. The ADC consumes 7.0mW from a single 0.85V supply, where 3.7mW is contributed by the reference buffer.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122576167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 6×5×4mm3 general purpose audio sensor node with a 4.7μW audio processing IC 一种6×5×4mm3通用音频传感器节点，带有4.7μW音频处理IC
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008521
Minchang Cho, Sechang Oh, Seokhyeon Jeong, Yiqun Zhang, Inhee Lee, Yejoong Kim, Li-Xuan Chuo, Dongkwun Kim, Qing Dong, Yen-Po Chen, M. Lim, M. Daneman, D. Blaauw, D. Sylvester, Hun-Seok Kim
{"title":"A 6×5×4mm3 general purpose audio sensor node with a 4.7μW audio processing IC","authors":"Minchang Cho, Sechang Oh, Seokhyeon Jeong, Yiqun Zhang, Inhee Lee, Yejoong Kim, Li-Xuan Chuo, Dongkwun Kim, Qing Dong, Yen-Po Chen, M. Lim, M. Daneman, D. Blaauw, D. Sylvester, Hun-Seok Kim","doi":"10.23919/VLSIC.2017.8008521","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008521","url":null,"abstract":"We present a complete, fully functional energy-autonomous audio sensor node with 6×5×4mm3 form factor. The system uses a new audio processing IC integrated with a MEMS microphone, general purpose 32-bit processor, 8Mb Flash, RF transceiver with custom 3D antenna, PV cells for energy harvesting and battery. The 4.7μW audio processing IC performs audio acquisition with 4–32× compression. The complete stand-alone system achieves 38mins of speech recording and energy-autonomous operation in room light.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122582232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
FMAX/VMIN and noise margin impacts of aging on domino read, static write, and retention of 8T 1R1W SRAM arrays in 22nm high-k/metal-gate tri-gate CMOS 老化对22nm高k/金属栅三栅CMOS中8T 1R1W SRAM阵列多米诺骨牌读、静态写和保持的FMAX/VMIN和噪声裕度影响
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008571
Jaydeep P. Kulkami, Carlos Tokunaga, M. Cho, M. Khellah, J. Tschanz, V. De
{"title":"FMAX/VMIN and noise margin impacts of aging on domino read, static write, and retention of 8T 1R1W SRAM arrays in 22nm high-k/metal-gate tri-gate CMOS","authors":"Jaydeep P. Kulkami, Carlos Tokunaga, M. Cho, M. Khellah, J. Tschanz, V. De","doi":"10.23919/VLSIC.2017.8008571","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008571","url":null,"abstract":"Progressive impacts of aging on Fmax & noise margin of the precharge-evaluate domino read, and VMIN for differential static write & retention are demonstrated via statistical measurements over the operational lifetime of a 14KB 1R1W 8T SRAM array in 22nm high-k/metal-gate tri-gate CMOS.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"317 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116292215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A true two-quadrant fully integrated switched capacitor DC-DC converter supporting vertically stacked DVS-loads with up to 99.6% efficiency 一个真正的两象限完全集成的开关电容DC-DC转换器，支持垂直堆叠的dvs负载，效率高达99.6%
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008486
Athanasios Sarafianos, M. Steyaert
{"title":"A true two-quadrant fully integrated switched capacitor DC-DC converter supporting vertically stacked DVS-loads with up to 99.6% efficiency","authors":"Athanasios Sarafianos, M. Steyaert","doi":"10.23919/VLSIC.2017.8008486","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008486","url":null,"abstract":"This paper presents a Switched Capacitor DC-DC converter capable of powering two vertically stacked loads, unlocking efficiencies of up to 99.6% when loads consume identical current. Furthermore, this converter is the first to provide up to 100% current imbalance thanks to its true two-quadrant operation, allowing loads to completely turn off. The system has been fabricated in a 65nm GP process followed by validation through measurements of its high efficiencies (>90% when δI<0.4) and control loop operation.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127080934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A resistor-free 4.266 Gbps LPDDR4 I/O in 10 nm FinFET CMOS technology 采用10nm FinFET CMOS技术的无电阻4.266 Gbps LPDDR4 I/O
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008478
T. Lu, M. Hsieh, Tien-Chien Huang, Chin-Ming Fu, Chih-Hsien Chang, K. Hsieh
{"title":"A resistor-free 4.266 Gbps LPDDR4 I/O in 10 nm FinFET CMOS technology","authors":"T. Lu, M. Hsieh, Tien-Chien Huang, Chin-Ming Fu, Chih-Hsien Chang, K. Hsieh","doi":"10.23919/VLSIC.2017.8008478","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008478","url":null,"abstract":"This paper presents a 4.266 Gbps LPDDR4 I/O with resistor-free on-die termination (ODT). The resistor-free ODT utilizes resistor-free driving unit (RFDU) with adaptive bias unit (ABU). The ABU adopts source-follower based structure which provides an adaptive bias voltage to compensate the saturated ID current caused non-linearity. The proposed LPDDR4 I/O is fabricated in 10 nm FinFET technology with the post-driver area of 0.0025mm2. The measurement result shows that the calibrated ODT resistances among 63 dies all meet LPDDR4 specifications. Furthermore, the eye opening of 0.73 UI is achieved with 4.266 Gbps PRBS pattern.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122851369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT 一款65nm 1.0 V 1.84 ns SOTB嵌入式SRAM，待机功率为13.72 nW/Mbit，适用于智能物联网
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIT.2017.7998145
M. Yabuuchi, K. Nii, S. Tanaka, Y. Shinozaki, Yoshiki Yamamoto, T. Hasegawa, H. Shinkawata, S. Kamohara
{"title":"A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT","authors":"M. Yabuuchi, K. Nii, S. Tanaka, Y. Shinozaki, Yoshiki Yamamoto, T. Hasegawa, H. Shinkawata, S. Kamohara","doi":"10.23919/VLSIT.2017.7998145","DOIUrl":"https://doi.org/10.23919/VLSIT.2017.7998145","url":null,"abstract":"A 65-nm Silicon-on-Thin-Box (SOTB) embedded SRAM is demonstrated. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit ultra-low standby power is observed, which is reduced to 1/1000 compared to the normal standby mode. The measured read access time with forward BB is 1.84 ns at 1.0 V overdrive and 25°C, which is improved by 60% and thus we achieved over 380 MHz operation. Up to 20% active read power reduction is also achieved by using proposed localized adoptive wordline width control.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124544398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.61 e-noise global shutter CMOS image sensor with two-stage charge transfer pixels 一种具有两级电荷转移像素的0.61 e噪声全局快门CMOS图像传感器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008497
K. Yasutomi, M. Seo, M. Kamoto, N. Teranishi, S. Kawahito
{"title":"A 0.61 e-noise global shutter CMOS image sensor with two-stage charge transfer pixels","authors":"K. Yasutomi, M. Seo, M. Kamoto, N. Teranishi, S. Kawahito","doi":"10.23919/VLSIC.2017.8008497","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008497","url":null,"abstract":"A low-noise global shutter (GS) CMOS image sensor (CIS) with two-stage charge transfer (2-CT) structure is presented. The low-noise wide dynamic range performance of the proposed pixel has been demonstrated by using column-parallel folding integration (FI)/cyclic ADCs. The GS image sensor with 5.6μm-pitch 1200 × 900 pixels is implemented with a 0.11 μm CIS technology. The noise and dynamic range are measured to be 0.61 e−rms and 81 dB, respectively.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129005450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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