A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET

2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI:10.23919/VLSIC.2017.8008506

D. Luu, L. Kull, T. Toifl, C. Menolfi, M. Braendli, P. Francese, T. Morf, M. Kossel, Hazar Yueksel, A. Cevrero, I. Ozkaya, Qiuting Huang

引用次数: 7

Abstract

A 300MS/s 12b SAR ADC achieving 61.6dB peak SNDR is presented. It reaches 60.5dB SNDR and 78.7dB SFDR with 0.8Vpp,diff input amplitude at Nyquist. The key elements are a comparator with inverter-based preamplifier and a SAR-based common-mode regulation. The regulation adjusts the common mode on a sample-by-sample basis to improve common-mode rejection. The ADC consumes 7.0mW from a single 0.85V supply, where 3.7mW is contributed by the reference buffer.

查看原文本刊更多论文

一种12b 61dB SNDR 300MS/s SAR ADC，具有基于逆变器的前置放大器和14nm CMOS FinFET共模调节DAC

提出了一种峰值信噪比为61.6dB的300MS/s 12b SAR ADC。在奈奎斯特差分输入幅值0.8Vpp时，SNDR达到60.5dB, SFDR达到78.7dB。关键元件是一个基于逆变器的前置放大器的比较器和一个基于sar的共模调节。该规则在逐个样品的基础上调整共模，以改善共模抑制。ADC从单个0.85V电源中消耗7.0mW，其中3.7mW由参考缓冲器贡献。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2017 Symposium on VLSI Circuits

自引率

0.00%

发文量