A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET

Abstract

A sampling phase detector (SPD) based PLL is presented. The high gain of this programmable SPD suppresses PLL's in-band noise and controls its bandwidth. Instead of sampling the VCO output directly like sub-sampling PLLs, the output of the frequency divider is sampled. This improves capture range and eases high frequency design while maintaining in-band noise reduction. The design uses a single charge pump based frequency acquisition technique with programmability for robust operation. The PLL is realized in a 16nm FinFET process. The SPD improves the measured inband phase noise from −90.6dBc/Hz to −104.1dBc/Hz at 18GHz with RMS jitter of 164fs when integrated over 10KHz–100MHz, while consuming 29.2mW. 2X frequency range of 9-to-18GHz is demonstrated using two LC VCOs.