T. Lu, M. Hsieh, Tien-Chien Huang, Chin-Ming Fu, Chih-Hsien Chang, K. Hsieh
{"title":"采用10nm FinFET CMOS技术的无电阻4.266 Gbps LPDDR4 I/O","authors":"T. Lu, M. Hsieh, Tien-Chien Huang, Chin-Ming Fu, Chih-Hsien Chang, K. Hsieh","doi":"10.23919/VLSIC.2017.8008478","DOIUrl":null,"url":null,"abstract":"This paper presents a 4.266 Gbps LPDDR4 I/O with resistor-free on-die termination (ODT). The resistor-free ODT utilizes resistor-free driving unit (RFDU) with adaptive bias unit (ABU). The ABU adopts source-follower based structure which provides an adaptive bias voltage to compensate the saturated ID current caused non-linearity. The proposed LPDDR4 I/O is fabricated in 10 nm FinFET technology with the post-driver area of 0.0025mm2. The measurement result shows that the calibrated ODT resistances among 63 dies all meet LPDDR4 specifications. Furthermore, the eye opening of 0.73 UI is achieved with 4.266 Gbps PRBS pattern.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"219 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A resistor-free 4.266 Gbps LPDDR4 I/O in 10 nm FinFET CMOS technology\",\"authors\":\"T. Lu, M. Hsieh, Tien-Chien Huang, Chin-Ming Fu, Chih-Hsien Chang, K. Hsieh\",\"doi\":\"10.23919/VLSIC.2017.8008478\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 4.266 Gbps LPDDR4 I/O with resistor-free on-die termination (ODT). The resistor-free ODT utilizes resistor-free driving unit (RFDU) with adaptive bias unit (ABU). The ABU adopts source-follower based structure which provides an adaptive bias voltage to compensate the saturated ID current caused non-linearity. The proposed LPDDR4 I/O is fabricated in 10 nm FinFET technology with the post-driver area of 0.0025mm2. The measurement result shows that the calibrated ODT resistances among 63 dies all meet LPDDR4 specifications. Furthermore, the eye opening of 0.73 UI is achieved with 4.266 Gbps PRBS pattern.\",\"PeriodicalId\":176340,\"journal\":{\"name\":\"2017 Symposium on VLSI Circuits\",\"volume\":\"219 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2017.8008478\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008478","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A resistor-free 4.266 Gbps LPDDR4 I/O in 10 nm FinFET CMOS technology
This paper presents a 4.266 Gbps LPDDR4 I/O with resistor-free on-die termination (ODT). The resistor-free ODT utilizes resistor-free driving unit (RFDU) with adaptive bias unit (ABU). The ABU adopts source-follower based structure which provides an adaptive bias voltage to compensate the saturated ID current caused non-linearity. The proposed LPDDR4 I/O is fabricated in 10 nm FinFET technology with the post-driver area of 0.0025mm2. The measurement result shows that the calibrated ODT resistances among 63 dies all meet LPDDR4 specifications. Furthermore, the eye opening of 0.73 UI is achieved with 4.266 Gbps PRBS pattern.