一种用于蓝牙LE的0.5V 1.6mW 2.4GHz分数n全数字锁相环,具有pvt不敏感的TDC,采用28nm CMOS开关电容倍频器

F. Kuo, Seyednaser Pourmousavian, T. Siriburanon, Ron Chen, Lan-chou Cho, C. Jou, F. Hsueh, R. Staszewski
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引用次数: 12

摘要

本文提出了一种由0.5 V单电源供电的超低电压分数n全数字锁相环(ADPLL)。当它的DCO直接工作在0.5 V时,一个开关电容DC-DC转换器将所有数字电路的电源电压提高一倍,并调节TDC电源以稳定其分辨率,从而在pvt上保持固定的带内相位噪声(PN)。ADPLL支持2点调制并形成蓝牙LE (BLE)发射器,实现在28 nm CMOS中。它的带内PN为−106 dBc/Hz (FoM为−239.2 dB), RMS抖动为0.86ps,参考频率为40 MHz时的功耗仅为1.6mW。当DCO切换为开环时,在BLE传输过程中功耗降至0.8 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 0.5V 1.6mW 2.4GHz fractional-N all-digital PLL for Bluetooth LE with PVT-insensitive TDC using switched-capacitor doubler in 28nm CMOS
This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation and forms a Bluetooth LE (BLE) transmitter realized in 28 nm CMOS. It achieves in-band PN of −106 dBc/Hz (FoM of −239.2 dB) and RMS jitter of 0.86ps while dissipating only 1.6mW at 40 MHz reference. The power consumption reduces to 0.8 mW during BLE transmission when the DCO switches to open-loop.
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