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2017 Symposium on VLSI Circuits最新文献

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A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop 具有轨对轨摆环振荡器和宽带噪声抑制环路的电源噪声不敏感锁相环
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008473
Dongin Kim, Seonghwan Cho
{"title":"A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop","authors":"Dongin Kim, Seonghwan Cho","doi":"10.23919/VLSIC.2017.8008473","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008473","url":null,"abstract":"This paper presents a supply noise insensitive digital phase-locked loop (PLL) using a wide bandwidth noise suppression loop (NSL). Unlike previous techniques using regulation or calibration on the voltage-controlled oscillator (VCO) that lead to voltage headroom reduction, the proposed approach employs a wide bandwidth feedback loop around the oscillator, which suppresses supply noise without any headroom loss. The proposed dual loop PLL is implemented in 65nm CMOS, achieving spur suppression of about 30dB near PLL loop bandwidth, while consuming 2.73mW at 3.2GHz output.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117028701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS 一个16位16MS/s SAR ADC，采用55nm CMOS片上校准
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008509
Junhua Shen, A. Shikata, Lalinda D. Fernando, Ned Guthrie, Baozhen Chen, Mark Maddox, Nikhil Mascarenhas, Ron Kapusta, M. Coln
{"title":"A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS","authors":"Junhua Shen, A. Shikata, Lalinda D. Fernando, Ned Guthrie, Baozhen Chen, Mark Maddox, Nikhil Mascarenhas, Ron Kapusta, M. Coln","doi":"10.23919/VLSIC.2017.8008509","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008509","url":null,"abstract":"This paper presents a SAR ADC that is much smaller and faster than the recently reported precision (16-bit and beyond) SAR ADCs [1, 2, 3]. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference switching using reservoir capacitors to improve speed and reduce area, LSB repeats and ADC residue measurement to improve efficiency. The prototype achieves 97.5dB SFDR while operating at 16MS/s and consumes 16.3mW. It was fabricated in 55nm CMOS and occupies 0.55mm2.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116282891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A shutter-less micro-bolometer thermal imaging system using multiple digital correlated double sampling for mobile applications 一种无快门微辐射热计热成像系统，使用多个数字相关双采样用于移动应用
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008577
Seunghyun Park, Tei Cho, Minsik Kim, Hyungchul Park, Kwyro Lee
{"title":"A shutter-less micro-bolometer thermal imaging system using multiple digital correlated double sampling for mobile applications","authors":"Seunghyun Park, Tei Cho, Minsik Kim, Hyungchul Park, Kwyro Lee","doi":"10.23919/VLSIC.2017.8008577","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008577","url":null,"abstract":"A micro-bolometer focal plane array (MBFPA)-based long wavelength Infra-red thermal imaging sensor is presented. The proposed multiple digital correlated double sampling (MD-CDS) readout method employing newly designed reference-cell greatly reduces PVT variation-induced fixed pattern noise (FPN) and as a result features much relaxed calibration process, easier TEC-less operation and Shutter-less operation. The readout IC and MBFPA was fabricated in 0.35um CMOS and amorphous silicon MEMS process respectively. The fabricated MBFPA thermal imaging sensor has NETD performance of 0.1 kelvin even though the mechanical shutter is not used.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A heterogeneous microprocessor for energy-scalable sensor inference using genetic programming 基于遗传规划的能量可伸缩传感器推理异构微处理器
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008535
Hongyang Jia, Jie Lu, N. Jha, Naveen Yerma
{"title":"A heterogeneous microprocessor for energy-scalable sensor inference using genetic programming","authors":"Hongyang Jia, Jie Lu, N. Jha, Naveen Yerma","doi":"10.23919/VLSIC.2017.8008535","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008535","url":null,"abstract":"We present a heterogeneous microprocessor for IoE sensor-inference applications, which achieves programmability required for feature extraction strictly using application data. Acceleration, though key for energy efficiency, poses substantial programmability challenges. These are overcome by exploiting genetic programming (GP) for automatic program synthesis. GP yields highly structured models of computation, enabling: (1) high degree of specialization; (2) systematic mapping of programs to the accelerator; and (3) energy scalability via user-controllable approximation. The microprocessor (130nm) achieves 325×/156× energy reduction, and farther 20x/9x energy scalability, for programmable feature extraction in two medical-sensor applications (seizure/arrhythmia-detection) vs. GP-model execution on CPU. The energy efficiency is 220 GOPS/W, near that of fixed-function accelerators, exceeding typical programmable accelerators.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122133609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 12.4pJ/cycle sub-threshold, 16pJ/cycle near-threshold ARM Cortex-M0+ MCU with autonomous SRPG/DVFS and temperature tracking clocks 一个12.4pJ/周期亚阈值，16pJ/周期近阈值ARM Cortex-M0+单片机，具有自主SRPG/DVFS和温度跟踪时钟
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008529
James Myers, Anand Savanth, Pranay Prabhat, Sheng Yang, Rohan Gaddh, S. Toh, D. Flynn
{"title":"A 12.4pJ/cycle sub-threshold, 16pJ/cycle near-threshold ARM Cortex-M0+ MCU with autonomous SRPG/DVFS and temperature tracking clocks","authors":"James Myers, Anand Savanth, Pranay Prabhat, Sheng Yang, Rohan Gaddh, S. Toh, D. Flynn","doi":"10.23919/VLSIC.2017.8008529","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008529","url":null,"abstract":"IoT requirements are almost as varied as the Things to which they are applied, but common demands are maximum battery life with minimum system cost and physical volume. Sub-threshold operation is promising, but even a single un-optimized or always-on component can eliminate low-voltage gains elsewhere. This work presents a highly integrated sub-threshold capable ARM based MCU with fully integrated multi-mode IVR, always-on power control, and on-chip clock sources, achieving 12.44pJ/cycle active energy (6.3pJ/cycle ideal), 139.4nW standby power (46nW ideal) and 1μW ULPBench power. Simple adaptive circuits are demonstrated to be efficient and correct for standby IVR and active system clocks across 0–70°C.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125797805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 256 energy bin spectrum X-ray photon-counting image sensor providing 8Mcounts/s/pixel and on-chip charge sharing, charge induction and pile-up corrections 一个256能量的bin谱x射线光子计数图像传感器，提供8Mcounts/s/pixel和片上电荷共享、电荷感应和堆积校正
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008496
A. Peizerat, J. Rostaing, P. Ouvrier-Buffet, S. Stanchina, P. Radisson, E. Marche
{"title":"A 256 energy bin spectrum X-ray photon-counting image sensor providing 8Mcounts/s/pixel and on-chip charge sharing, charge induction and pile-up corrections","authors":"A. Peizerat, J. Rostaing, P. Ouvrier-Buffet, S. Stanchina, P. Radisson, E. Marche","doi":"10.23919/VLSIC.2017.8008496","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008496","url":null,"abstract":"To achieve better and faster material discrimination in applications like security inspection, X-Ray image sensors giving a highly resolved energy spectrum per pixel are required. In this paper, a new pixel architecture for spectral imaging is presented, exhibiting a 256 bin spectrum per pixel in a single image duration, up to two orders of magnitude higher than previous works. A prototype circuit, composed of 4×8 pixels of 756μm×800μm and hybridized to a CdTe crystal, was fabricated in a 0.13μm process. Our pixel architecture has been measured at 8 Mcounts/s/pixel while embedding on-chip charge sharing, charge induction and pile-up corrections.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126964800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 5GS/s 156MHz BW 70dB DR continuous-time sigma-delta modulator with time-interleaved reference data-weighted averaging 5GS/s 156MHz BW 70dB DR连续时间sigma-delta调制器，具有时间交错参考数据加权平均
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008539
M. B. Dayanik, Daniel Weyer, M. Flynn
{"title":"A 5GS/s 156MHz BW 70dB DR continuous-time sigma-delta modulator with time-interleaved reference data-weighted averaging","authors":"M. B. Dayanik, Daniel Weyer, M. Flynn","doi":"10.23919/VLSIC.2017.8008539","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008539","url":null,"abstract":"Conventional dynamic element matching limits the continuous time ΣΔ ADC architecture at high speeds. This work introduces a Time-Interleaved Reference Data-Weighted-Averaging (TI-RDWA) architecture that breaks the speed limitation of the traditional DEM decoder. Time-interleaving eliminates the reference voltage settling bottleneck, enabling DWA operation at 5 GHz, while still achieving the benefits of first order shaping of feedback DAC mismatch. The prototype 5GS/s ADC has 70dB and 84dB measured dynamic range and SFDR, respectively, in a 156MHz bandwidth. TI-RDWA improves SFDR by 17dB. The 40nm CMOS prototype consumes 233mW.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130593255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS 9.1 enob21.7 fj /转换步长10b 500MS/s单通道流水线SAR ADC，带电流模式精细ADC, 28nm CMOS
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008560
Kyoung-Jun Moon, Hyun-Wook Kang, Dong-Shin Jo, Mi-Young Kim, Seung-Yeob Baek, Michael Choi, H. Ko, S. Ryu
{"title":"A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS","authors":"Kyoung-Jun Moon, Hyun-Wook Kang, Dong-Shin Jo, Mi-Young Kim, Seung-Yeob Baek, Michael Choi, H. Ko, S. Ryu","doi":"10.23919/VLSIC.2017.8008560","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008560","url":null,"abstract":"A single-channel 10b pipelined SAR ADC with a gm-cell residue amplifier and a current-mode fine SAR ADC achieves a 500MS/s conversion rate in a 28nm CMOS process under a 1.0 V supply. With background offset and gain calibration, the prototype ADC achieves an SNDR of 56.6dB at Nyquist. With power consumption of 6mW, it obtains a FoM of 21.7fJ/conversion-step.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122345092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 2.25-mW/Gb/s 80-Gb/s-PAM4 linear driver with a single supply using stacked current-mode architecture in 65-nm CMOS 2.25 mw /Gb/s 80 Gb/s- pam4单电源线性驱动器，采用65纳米CMOS堆叠电流模式架构
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008525
S. Nakano, M. Nagatani, M. Nogawa, Y. Kawamura, K. Kikuchi, K. Tsuzuki, H. Nosaka
{"title":"A 2.25-mW/Gb/s 80-Gb/s-PAM4 linear driver with a single supply using stacked current-mode architecture in 65-nm CMOS","authors":"S. Nakano, M. Nagatani, M. Nogawa, Y. Kawamura, K. Kikuchi, K. Tsuzuki, H. Nosaka","doi":"10.23919/VLSIC.2017.8008525","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008525","url":null,"abstract":"This paper presents a low-power linear driver for a coherent optical transmitter. We propose a driver using stacked current-mode architecture to achieve low-power consumption with a single supply. The driver can drive from 25 to 50 Ω impedances with almost the same output waveforms by using a variable equalizer and adjusting the current of the post-amplifier. The proposed driver was fabricated in 65-nm CMOS technology and achieved the power efficiency of 3.6 mW/Gb/s with a differential output swing of 2.9 Vpp for a 50-Gb/s NRZ signal and 2.25 mW/Gb/s with a differential output swing of 2.0 Vpp for an 80-Gb/s PAM4 signal.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126066186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET 基于14nm CMOS FinFET的低延迟数字CDR 60gb /s 1.9 pJ/bit NRZ光接收机
2017 Symposium on VLSI Circuits Pub Date : 2017-06-01 DOI: 10.23919/VLSIC.2017.8008524
A. Cevrero, I. Ozkaya, P. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, M. Kossel, L. Kull, D. Luu, J. Proesel, Y. Leblebici, T. Toifl
{"title":"A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET","authors":"A. Cevrero, I. Ozkaya, P. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, M. Kossel, L. Kull, D. Luu, J. Proesel, Y. Leblebici, T. Toifl","doi":"10.23919/VLSIC.2017.8008524","DOIUrl":"https://doi.org/10.23919/VLSIC.2017.8008524","url":null,"abstract":"This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low-complexity control logic suitable for high-speed applications. Multi-phase clock signals that drive data/edge slicers are created by an open loop quadrature clock generator. The circuit, characterized in an 850nm VCSEL based optical link, recovers PRBS7 data (BER<10−12) at 60Gb/s with a frequency tracking range of ±600ppm. The measured sinusoidal JTOL indicates a corner frequency of 80MHz, with high frequency JTOL of 0.16UIpp at −5dBm optical modulation amplitude (OMA). The RX energy efficiency is 1.9pJ/bit.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121089278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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