A. Cevrero, I. Ozkaya, P. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, M. Kossel, L. Kull, D. Luu, J. Proesel, Y. Leblebici, T. Toifl
{"title":"基于14nm CMOS FinFET的低延迟数字CDR 60gb /s 1.9 pJ/bit NRZ光接收机","authors":"A. Cevrero, I. Ozkaya, P. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, M. Kossel, L. Kull, D. Luu, J. Proesel, Y. Leblebici, T. Toifl","doi":"10.23919/VLSIC.2017.8008524","DOIUrl":null,"url":null,"abstract":"This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low-complexity control logic suitable for high-speed applications. Multi-phase clock signals that drive data/edge slicers are created by an open loop quadrature clock generator. The circuit, characterized in an 850nm VCSEL based optical link, recovers PRBS7 data (BER<10−12) at 60Gb/s with a frequency tracking range of ±600ppm. The measured sinusoidal JTOL indicates a corner frequency of 80MHz, with high frequency JTOL of 0.16UIpp at −5dBm optical modulation amplitude (OMA). The RX energy efficiency is 1.9pJ/bit.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET\",\"authors\":\"A. Cevrero, I. Ozkaya, P. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, M. Kossel, L. Kull, D. Luu, J. Proesel, Y. Leblebici, T. Toifl\",\"doi\":\"10.23919/VLSIC.2017.8008524\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low-complexity control logic suitable for high-speed applications. Multi-phase clock signals that drive data/edge slicers are created by an open loop quadrature clock generator. The circuit, characterized in an 850nm VCSEL based optical link, recovers PRBS7 data (BER<10−12) at 60Gb/s with a frequency tracking range of ±600ppm. The measured sinusoidal JTOL indicates a corner frequency of 80MHz, with high frequency JTOL of 0.16UIpp at −5dBm optical modulation amplitude (OMA). The RX energy efficiency is 1.9pJ/bit.\",\"PeriodicalId\":176340,\"journal\":{\"name\":\"2017 Symposium on VLSI Circuits\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2017.8008524\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008524","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET
This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low-complexity control logic suitable for high-speed applications. Multi-phase clock signals that drive data/edge slicers are created by an open loop quadrature clock generator. The circuit, characterized in an 850nm VCSEL based optical link, recovers PRBS7 data (BER<10−12) at 60Gb/s with a frequency tracking range of ±600ppm. The measured sinusoidal JTOL indicates a corner frequency of 80MHz, with high frequency JTOL of 0.16UIpp at −5dBm optical modulation amplitude (OMA). The RX energy efficiency is 1.9pJ/bit.