S. Nakano, M. Nagatani, M. Nogawa, Y. Kawamura, K. Kikuchi, K. Tsuzuki, H. Nosaka
{"title":"A 2.25-mW/Gb/s 80-Gb/s-PAM4 linear driver with a single supply using stacked current-mode architecture in 65-nm CMOS","authors":"S. Nakano, M. Nagatani, M. Nogawa, Y. Kawamura, K. Kikuchi, K. Tsuzuki, H. Nosaka","doi":"10.23919/VLSIC.2017.8008525","DOIUrl":null,"url":null,"abstract":"This paper presents a low-power linear driver for a coherent optical transmitter. We propose a driver using stacked current-mode architecture to achieve low-power consumption with a single supply. The driver can drive from 25 to 50 Ω impedances with almost the same output waveforms by using a variable equalizer and adjusting the current of the post-amplifier. The proposed driver was fabricated in 65-nm CMOS technology and achieved the power efficiency of 3.6 mW/Gb/s with a differential output swing of 2.9 Vpp for a 50-Gb/s NRZ signal and 2.25 mW/Gb/s with a differential output swing of 2.0 Vpp for an 80-Gb/s PAM4 signal.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008525","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper presents a low-power linear driver for a coherent optical transmitter. We propose a driver using stacked current-mode architecture to achieve low-power consumption with a single supply. The driver can drive from 25 to 50 Ω impedances with almost the same output waveforms by using a variable equalizer and adjusting the current of the post-amplifier. The proposed driver was fabricated in 65-nm CMOS technology and achieved the power efficiency of 3.6 mW/Gb/s with a differential output swing of 2.9 Vpp for a 50-Gb/s NRZ signal and 2.25 mW/Gb/s with a differential output swing of 2.0 Vpp for an 80-Gb/s PAM4 signal.