{"title":"5GS/s 156MHz BW 70dB DR连续时间sigma-delta调制器，具有时间交错参考数据加权平均","authors":"M. B. Dayanik, Daniel Weyer, M. Flynn","doi":"10.23919/VLSIC.2017.8008539","DOIUrl":null,"url":null,"abstract":"Conventional dynamic element matching limits the continuous time ΣΔ ADC architecture at high speeds. This work introduces a Time-Interleaved Reference Data-Weighted-Averaging (TI-RDWA) architecture that breaks the speed limitation of the traditional DEM decoder. Time-interleaving eliminates the reference voltage settling bottleneck, enabling DWA operation at 5 GHz, while still achieving the benefits of first order shaping of feedback DAC mismatch. The prototype 5GS/s ADC has 70dB and 84dB measured dynamic range and SFDR, respectively, in a 156MHz bandwidth. TI-RDWA improves SFDR by 17dB. The 40nm CMOS prototype consumes 233mW.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A 5GS/s 156MHz BW 70dB DR continuous-time sigma-delta modulator with time-interleaved reference data-weighted averaging\",\"authors\":\"M. B. Dayanik, Daniel Weyer, M. Flynn\",\"doi\":\"10.23919/VLSIC.2017.8008539\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Conventional dynamic element matching limits the continuous time ΣΔ ADC architecture at high speeds. This work introduces a Time-Interleaved Reference Data-Weighted-Averaging (TI-RDWA) architecture that breaks the speed limitation of the traditional DEM decoder. Time-interleaving eliminates the reference voltage settling bottleneck, enabling DWA operation at 5 GHz, while still achieving the benefits of first order shaping of feedback DAC mismatch. The prototype 5GS/s ADC has 70dB and 84dB measured dynamic range and SFDR, respectively, in a 156MHz bandwidth. TI-RDWA improves SFDR by 17dB. The 40nm CMOS prototype consumes 233mW.\",\"PeriodicalId\":176340,\"journal\":{\"name\":\"2017 Symposium on VLSI Circuits\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2017.8008539\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008539","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 5GS/s 156MHz BW 70dB DR continuous-time sigma-delta modulator with time-interleaved reference data-weighted averaging
Conventional dynamic element matching limits the continuous time ΣΔ ADC architecture at high speeds. This work introduces a Time-Interleaved Reference Data-Weighted-Averaging (TI-RDWA) architecture that breaks the speed limitation of the traditional DEM decoder. Time-interleaving eliminates the reference voltage settling bottleneck, enabling DWA operation at 5 GHz, while still achieving the benefits of first order shaping of feedback DAC mismatch. The prototype 5GS/s ADC has 70dB and 84dB measured dynamic range and SFDR, respectively, in a 156MHz bandwidth. TI-RDWA improves SFDR by 17dB. The 40nm CMOS prototype consumes 233mW.
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