Hyun-Gi Seok, Oh-Yong Jung, Anjana Dissanayake, Sang-Gug Lee
{"title":"2.4GHz，−102dbm灵敏度，25kb/s, 0.466mW抗干扰BFSK多通道滑动中频ULP接收机","authors":"Hyun-Gi Seok, Oh-Yong Jung, Anjana Dissanayake, Sang-Gug Lee","doi":"10.23919/VLSIC.2017.8008552","DOIUrl":null,"url":null,"abstract":"This paper presents an ultra-low power, high-sensitivity, and interference-resistant receiver suitable for IoT applications. By the combination of sliding-IF based low-power down-conversion and relative-power-detection based FSK demodulation, the proposed receiver achieves multi-channel operation and minimizes power consumption. Cascaded N-path filter and 4th-order hybrid-PPF are adopted to improve the sensitivity and carrier-to-interference ratio. Implemented in a 65nm CMOS, the receiver achieves −102dBm sensitivity at 0.1% BER and 25kb/s data rate while consuming 466μW from a 0.6V supply.","PeriodicalId":176340,"journal":{"name":"2017 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 2.4GHz, −102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver\",\"authors\":\"Hyun-Gi Seok, Oh-Yong Jung, Anjana Dissanayake, Sang-Gug Lee\",\"doi\":\"10.23919/VLSIC.2017.8008552\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an ultra-low power, high-sensitivity, and interference-resistant receiver suitable for IoT applications. By the combination of sliding-IF based low-power down-conversion and relative-power-detection based FSK demodulation, the proposed receiver achieves multi-channel operation and minimizes power consumption. Cascaded N-path filter and 4th-order hybrid-PPF are adopted to improve the sensitivity and carrier-to-interference ratio. Implemented in a 65nm CMOS, the receiver achieves −102dBm sensitivity at 0.1% BER and 25kb/s data rate while consuming 466μW from a 0.6V supply.\",\"PeriodicalId\":176340,\"journal\":{\"name\":\"2017 Symposium on VLSI Circuits\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2017.8008552\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2017.8008552","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents an ultra-low power, high-sensitivity, and interference-resistant receiver suitable for IoT applications. By the combination of sliding-IF based low-power down-conversion and relative-power-detection based FSK demodulation, the proposed receiver achieves multi-channel operation and minimizes power consumption. Cascaded N-path filter and 4th-order hybrid-PPF are adopted to improve the sensitivity and carrier-to-interference ratio. Implemented in a 65nm CMOS, the receiver achieves −102dBm sensitivity at 0.1% BER and 25kb/s data rate while consuming 466μW from a 0.6V supply.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
