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A feasibility study of on-wafer wireless testing 晶圆上无线测试的可行性研究
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542472
Piljae Park, C. Yue
{"title":"A feasibility study of on-wafer wireless testing","authors":"Piljae Park, C. Yue","doi":"10.1109/VDAT.2008.4542472","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542472","url":null,"abstract":"The feasibility of on-wafer wireless test is assessed in this paper. By replacing expensive high-frequency probe cards with wireless data link, testing cost can potentially be lowered. Key elements for wireless test at the wafer level include on-chip antenna and RF transceivers. A 24-GHz on-chip folded dipole antenna has been designed to fit in the scribe-lines between the silicon dies. The measured antenna gain shows -22.6 dBi. The power budget for a data link between a wafer with on-chip antenna and a tester equipped with high-gain horn antenna is presented. Our finding verifies that the required SNR and antenna bandwidth for wireless test can be achieved. Based on the measured antenna characteristics, several wireless test examples are illustrated.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115130999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 90nm 10-bit 1GS/s current-steering DAC with 1-V supply voltage 90nm 10位1GS/s电流转向DAC，电源电压为1v
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542461
Chueh-Hao Yu, Ching-Hsuan Hsieh, T. Shia, Wen-Tzao Chen
{"title":"A 90nm 10-bit 1GS/s current-steering DAC with 1-V supply voltage","authors":"Chueh-Hao Yu, Ching-Hsuan Hsieh, T. Shia, Wen-Tzao Chen","doi":"10.1109/VDAT.2008.4542461","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542461","url":null,"abstract":"This paper discusses the design of a 90 nm CMOS IV 10-bit lGS/s current-steering D/A converter. The proposed design operates under low supply voltage of IV and gives a large differential full- scale output of 0.5 Vppd. A wide full-scale current range of 2-10 mA is designed and the output impedance of the DAC is optimized for different full-scale currents by a bias circuit related to them. The post-layout simulation results show that the SFDR and ENOB are 50.64 dBc and 7.86 bit respectively with a full-scale 308.59 MHz input at lGS/s and more than 50 dB and 8 bit respectively when the signal bandwidth is less than 200 MHz. The converter consumes a total power of 23 mW at 1 V supply. It is designed for 90 nm CMOS technology and has an active area of 0.47 mm2.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121596760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Networks-In-Package: Performances management and design methodology 包内网络:性能管理和设计方法
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542432
A.M. Kouadri M, B. Senouci, F. Pétrot
{"title":"Networks-In-Package: Performances management and design methodology","authors":"A.M. Kouadri M, B. Senouci, F. Pétrot","doi":"10.1109/VDAT.2008.4542432","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542432","url":null,"abstract":"Nowadays large scale MPSoC designs embedding multiple processors, memories and specialized IPs require high integration densities which can not be met at an acceptable cost within the standard single-chip technology. The systems-in-package (SiP) approach has been proposed then as an alternative which enables such integration requirements. Even though analysis of systems-in-package design techniques shows large similarities with standard techniques for multi-chip-modules (MCM), there is a huge methodological lack for communication-centric MPSoCs. In this paper we motivate the need for new design methodologies which addresses the various problems of the emerging NiP (networks-in- package) paradigm with a special focus on performances considerations. We also propose a complete NoC architecture (MS-NoC) and a design flow aimed at helping designers to build NiP architectures.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125754005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Sensitivity-based multiple-Vt cell swapping for leakage power reduction 基于灵敏度的多vt电池交换降低泄漏功率
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542439
W. Lee, Hung-Yi Liu, Kuan-Hsien Ho, Yao-Wen Chang
{"title":"Sensitivity-based multiple-Vt cell swapping for leakage power reduction","authors":"W. Lee, Hung-Yi Liu, Kuan-Hsien Ho, Yao-Wen Chang","doi":"10.1109/VDAT.2008.4542439","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542439","url":null,"abstract":"With the technology advancement, leakage power has become a significant source of total power consumption, and thus it is desirable to develop effective leakage-power reduction techniques for power optimization. The sensitivity-based technique has been shown to be an efficient approach to leakage power reduction by swapping gates (cells) with different threshold voltages. Nevertheless, its solution quality is limited and unstable because the technique does not have a global view on the effects of the gate swapping on other gates. To remedy this weakness, we develop a novel sensitivity formulation with a more global view on the gate-swapping effects. We also develop two static-timing-analysis engines embedded in the proposed algorithm to improve the efficiency. Experimental results show that our algorithm can effectively reduce leakage power by up to 74.4%. Compared with the state-of-the-art sensitivity-based method, we can achieve more leakage-power reduction by up to 20.6% and consume less running time and memory. The results show the effectiveness and efficiency of our algorithm.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129782228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An OFDMA-based wireless body area network using frequency pre-calibration 一种基于ofdma的无线体域网络
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542445
H. Ma, J. Yu, Tsan-Wen Chen, Chien-Ying Yu, Chen-Yi Lee
{"title":"An OFDMA-based wireless body area network using frequency pre-calibration","authors":"H. Ma, J. Yu, Tsan-Wen Chen, Chien-Ying Yu, Chen-Yi Lee","doi":"10.1109/VDAT.2008.4542445","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542445","url":null,"abstract":"A rotator and synthesizer driven (RSD) frequency pre-calibration technique is proposed in this paper for the wireless body area network applications. To overcome the large carrier frequency offset (CFO) and sampling clock offset (SCO) due to a low-cost and low-precision reference clock, the CFO and SCO are estimated from the system downlink process. These estimated CFO and SCO values are provided to a rotator and a synthesizer for signal pre-processing. This RSD concept is evaluated in the proposed WiBoC OFDMA system. The tolerated CFO and SCO ranges are extended to 2.5x of existing wireless systems. This system is designed and simulated in a 90 nm technology with 77.5 muW computation power overhead.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129977966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
CMOS low-noise amplifier with shunt-peaking load for group 1∼3 MB-OFDM ultra-wideband wireless receiver 用于组1 ~ 3mb - ofdm超宽带无线接收机的带分流峰值负载的CMOS低噪声放大器
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542460
Zhe-Yang Huang, Che-Cheng Huang, Chun-Chieh Chen, C. Hung, C. Jou
{"title":"CMOS low-noise amplifier with shunt-peaking load for group 1∼3 MB-OFDM ultra-wideband wireless receiver","authors":"Zhe-Yang Huang, Che-Cheng Huang, Chun-Chieh Chen, C. Hung, C. Jou","doi":"10.1109/VDAT.2008.4542460","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542460","url":null,"abstract":"In this paper, a CMOS low-noise amplifier (LNA) is designed for ultra-wideband (UWB) wireless receiver system. The design consists of a wideband input impedance matching network, two stage cascode amplifiers with shunt-peaking load and an output buffer for measurement purpose. It was fabricated in UMC 0.18 mum standard RF CMOS process. The LNA provides 14.1 dB maximum power gain between 2.3G Hz-8.0 GH while consuming 18.6 mW (including buffer) through a 1.8 V supply. Over the 3.1 GHz-8.0 GHz frequency band, a minimum noise figure is 2.0 dB. The input return loss is lower than -7.1 dB in the entire bandwidth has also been achieved.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"49 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116318399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 93dB-ohm 2.5Gb/s CMOS burst-mode optical receiver with internal reset creation 内置复位创建的93dB-ohm 2.5Gb/s CMOS突发模式光接收器
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542436
Yiming Lin, Chia-Ming Tsai
{"title":"A 93dB-ohm 2.5Gb/s CMOS burst-mode optical receiver with internal reset creation","authors":"Yiming Lin, Chia-Ming Tsai","doi":"10.1109/VDAT.2008.4542436","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542436","url":null,"abstract":"This paper presents a 2.5 Gb/s burst-mode optical receiver with quick response in a 0.18 mum CMOS process. A dual-mode transimpedance amplifier is used to achieve a dynamic range of 19 dB. The internal reset signal created by the limiting amplifier is more reliable due to the increased net gain compared to prior designs. The receiver achieves 93 dBOmega total differential transimpedance gain, 1.56 GHz optical bandwidth, and fast response time of less than 10 ns. This IC dissipates 146 mW from a 1.8 V supply.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126767115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient analog signal processing in nm CMOS technologies 纳米CMOS技术中的高效模拟信号处理
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542395
W. Sansen
{"title":"Efficient analog signal processing in nm CMOS technologies","authors":"W. Sansen","doi":"10.1109/VDAT.2008.4542395","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542395","url":null,"abstract":"Summary form only given. In nanometer CMOS technologies, several new phenomena occur as a result of the shorter channel-lengths. The most important ones are velocity saturation and gate leakage currents. As a result analog signal processing suffers from reduced accuracy and more noise. Also the transconductance and speed are both limited by velocity saturation. Moreover the supply voltage has been reduced to values around 1 Volt, creating new challenges for analog signal processing. This presentation provides an overview of these phenomena. They are illustrated by a review of the most important building blocks for analog signal processing in nm CMOS technologies. Amplifiers and filters are discussed and compared based on generally accepted FOM (Figures of Merit). It is followed by an overview of sub-1 Volt circuits for various applications. Rail-to-rail amplifiers and amplifiers/filters configurations are given with both Gate and Bulk drives.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127451922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Logic diagnosis, yield learning and quality of test 逻辑诊断，产量学习和测试质量
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542397
J. Rajski
{"title":"Logic diagnosis, yield learning and quality of test","authors":"J. Rajski","doi":"10.1109/VDAT.2008.4542397","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542397","url":null,"abstract":"In the past, logic diagnosis was primarily used to support failure analysis labs. It was typically done on a small sample of defective chips, therefore long processing times, manual generation of diagnostic patterns, and usage of expensive equipment was acceptable. In addition to failure analysis, yield learning relied on test chips and in-line inspection. Recently, sub-wavelength lithography processes have started introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in the process. Test chips are no longer able to represent the various failure mechanisms originating from critical features. The number of such features is too large to properly represent it on silicon in a cost-effective manner. For new processes it is also impossible to predict all significant features up front. With the decreasing sizes of defects and increasing percentage of invisible ones, in-line inspection data is not always available.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129098379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory 高分辨率全数字锁相环及其应用于内存内置速度分级
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542464
H. Hsu, Chun-Chieh Tu, Shi-Yu Huang
{"title":"A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory","authors":"H. Hsu, Chun-Chieh Tu, Shi-Yu Huang","doi":"10.1109/VDAT.2008.4542464","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542464","url":null,"abstract":"In this paper we present a high-resolution and wide-range all-digital phase-locked loop (ADPLL), which is suitable to function as a clock generator. The digitally controlled oscillator (DCO) is able to operate from 70 to 725 MHz and achieves 5.2ps resolution. The phase-frequency detector (PFD) is designed using a latch-based sense amplifier, leading to a nearly perfect PFD that is able to resolve a phase difference as minute as only 1ps. In addition, we use this ADPLL as a vehicle to perform built-in speed grading (BISG) for memory. Combining a binary search process with multiple runs of built-in self-test (BIST), the maximum operating speed can thus be tracked down on the chip with a high precision.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132019372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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