2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献_第3页

Synthesis of a timing-error detection architecture 时序误差检测体系结构的综合

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542437

Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang

引用次数: 0

High throughput partially-parallel irregular LDPC decoder based on delta-value message-passing schedule 基于增量值消息传递调度的高吞吐量部分并行不规则LDPC解码器

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542452

Wen Ji, Xing Li, T. Ikenaga, S. Goto

引用次数: 0

Built-in jitter measurement methodology for spread-spectrum clock generators 扩频时钟发生器的内置抖动测量方法

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542414

Jen-Chien Hsu, Maohsuan Chou, C. Su

引用次数: 2

Phase noise testing of single chip TV tuners 单片机电视调谐器的相位噪声测试

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542473

Po-Chou Lin, Chao-Hsuan Hsu, J.C.-M. Li, Chih-Ming Chiang, C. Pan

引用次数: 0

A 1-GS/s CMOS 6-bit flash ADC with an offset calibrating method 1-GS/s CMOS 6位闪存ADC与偏移校准方法

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542455

C. Chang, Chih-Yi Hsiao, Ching-Yuan Yang

引用次数: 10

Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology 克服高速电路工艺变化的自适应偏置电路

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542458

Luis Chen, C. Yue

引用次数: 0

On-chip interconnection design and SoC integration with OCP 片上互连设计和SoC集成与OCP

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542404

Chih-Wea Wang, C. Lai, Chi-Feng Wu, Shih-Arn Hwang, Ying-Hsi Lin

引用次数: 23

A 4-PAM adaptive analog equalizer for backplane interconnections 用于背板互连的4-PAM自适应模拟均衡器

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542447

Yen-Chuan Huang, Qui-Ting Chen, Tai-Cheng Lee

引用次数: 5

Power and density-aware buffer insertion 功率和密度感知缓冲器插入

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542469

Yi-Ju Ho, Wai-Kei Mak

引用次数: 3

Temperature aware SoC design for reduced leakage power and enhanced reliability 温度感知SoC设计，减少泄漏功率，提高可靠性

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542398

M. Abadir, K. Khouri, A. Gupta

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引用次数: 0