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2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献

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An improved feature ranking method for diagnosis of systematic timing uncertainty 一种用于系统时序不确定性诊断的改进特征排序方法
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542422
P. Bastani, N. Callegari, L.-C. Wang, M. Abadir
{"title":"An improved feature ranking method for diagnosis of systematic timing uncertainty","authors":"P. Bastani, N. Callegari, L.-C. Wang, M. Abadir","doi":"10.1109/VDAT.2008.4542422","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542422","url":null,"abstract":"For diagnosis of systematic modeling uncertainty, an earlier work proposes a path-based methodology that employs support vector classification analysis to rank so-called delay entities. This work explains that delay entities can be seen as path features that are used to encode the characteristics of a path. We present an improved path feature ranking algorithm based on support vector epsiv-insensitive regression. We also discuss how to check if a dataset is too noisy for the analysis. Experimental results are presented to explain the ranking methodology and demonstrate the effectiveness of the improved approach.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114652466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 400-MHz super-regenerative receiver with digital calibration for capsule endoscope systems in 0.18-μm CMOS 用于0.18 μm CMOS胶囊内窥镜系统的400 mhz超再生数字校准接收机
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542408
Ching-Jen Tung, Yao-Hong Liu, Hui-Hsien Liu, Tsung-Hsien Lin
{"title":"A 400-MHz super-regenerative receiver with digital calibration for capsule endoscope systems in 0.18-μm CMOS","authors":"Ching-Jen Tung, Yao-Hong Liu, Hui-Hsien Liu, Tsung-Hsien Lin","doi":"10.1109/VDAT.2008.4542408","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542408","url":null,"abstract":"A low-power super-regenerative receiver (SR-RX) with a digitally-controlled oscillator for the capsule endoscope system is reported in this paper. In this work, an open-loop frequency calibration loop is proposed to adjust the oscillator center frequency to the desired frequency band. The RX operates in the 402-405 MHz MICS band, and is designed to receive on-off keying modulation signal. This chip was fabricated in the TSMC 0.18-mum CMOS process. The RX start-up time is only 14.8 mus and is capable of a maximum data rate of 1 Mbps. The SR-RX consumes 5.5 mW from a 1.5-V supply voltage.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127103319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Multiple error diagnosis in large combinational circuits using an efficient parallel vector simulation 基于高效并行矢量仿真的大型组合电路多错误诊断
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542424
Yu-Lin Hsiao, Chun-Yao Wang, Yung-Chih Chen
{"title":"Multiple error diagnosis in large combinational circuits using an efficient parallel vector simulation","authors":"Yu-Lin Hsiao, Chun-Yao Wang, Yung-Chih Chen","doi":"10.1109/VDAT.2008.4542424","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542424","url":null,"abstract":"This paper presents a parallel vector simulation-based approach to locating multiple errors in large combinational circuits. Two heuristics are proposed to avoid the explosion of the error space. Experimental results on a set of ISCAS'85 and two large benchmarks show that our approach efficiently identifies a small set of correctable nodes that contains the actual error sources. Thus, further error correction can be conducted on the erroneous implementation.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122912842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A complementary Colpitts VCO implemented with ring inductor 一种采用环形电感实现的互补性Colpitts压控振荡器
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542428
S. Jang, Chun-Yuan Chiu, Chien-Feng Lee
{"title":"A complementary Colpitts VCO implemented with ring inductor","authors":"S. Jang, Chun-Yuan Chiu, Chien-Feng Lee","doi":"10.1109/VDAT.2008.4542428","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542428","url":null,"abstract":"This paper presents a novel differential voltage controlled oscillator (VCO). The VCO uses a closed-loop ring inductor and is composed of two single-ended complementary Colpitts LC VCOs coupled by two identical inductors and is implemented in a standard 0.18 mum CMOS technology. This differential VCO operates at 5.76-6.76 GHz. The measured phase noise of the VCO operating at 6.7 GHz is -118.5 dBc/Hz at 1-MHz offset while the VCO draws 3.75 mA and 5.625 mW consumption from a supply voltage of 1.5 V.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127837274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Hardware realization of a medical diagnostic system based on Probabilistic CMOS (PCMOS) technology 基于概率CMOS (PCMOS)技术的医疗诊断系统的硬件实现
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542466
Z. Kong, Jun-Jie Tan, Bilge E. S. Akgul, K. Yeo, K. Palem, W. Goh
{"title":"Hardware realization of a medical diagnostic system based on Probabilistic CMOS (PCMOS) technology","authors":"Z. Kong, Jun-Jie Tan, Bilge E. S. Akgul, K. Yeo, K. Palem, W. Goh","doi":"10.1109/VDAT.2008.4542466","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542466","url":null,"abstract":"The continuous miniaturization of CMOS feature sizes into the nanometer regime has increasingly caused problems due to noise vulnerability, process variations, and energy consumption. Noise vulnerability and process variations have been recognized to cause statistical or probabilistic device behaviors. In this paper, by capitalizing on what most people termed as nuisance, we demonstrate how noise can be put to good use in CMOS devices. We present the first hardware implementation of a Bayesian medical diagnostic system for real-world patient monitoring using probabilistic CMOS (PCMOS). We explore ways to adapt Bayesian structure under realistic hardware constraints without compromising prediction accuracy. As compared to conventional CMOS, PCMOS implementation of the network offers noteworthy merits: ultra low-power consumption, high-speed performance and cost-effectiveness.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"01 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127423677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 62–66.1GHz phase-locked loop in 0.13um CMOS technology 基于0.13um CMOS技术的62-66.1GHz锁相环
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542425
Kun-Hung Tsai, Shen-Iuan Liu
{"title":"A 62–66.1GHz phase-locked loop in 0.13um CMOS technology","authors":"Kun-Hung Tsai, Shen-Iuan Liu","doi":"10.1109/VDAT.2008.4542425","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542425","url":null,"abstract":"This paper presents a 62-66.1 GHz phase-locked loop (PLL) in 0.13 um CMOS process. By employing a modified wide-range injection-locked frequency divider, the proposed PLL demonstrates the output frequency from 62 to 66.1 GHz which allowing wideband application in unlicensed 60 GHz radio. As the PLL operates at 66.09 GHz, the measured phase noise at 1 MHz offset is -74.5 dBc/Hz. The proposed circuit consumes a power of 89 mW from a 1.5 V supply voltage.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115735122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploiting capacitance in high-performance computer systems 在高性能计算机系统中利用电容
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542411
A. Chow, D. Hopkins, R. Drost, R. Ho
{"title":"Exploiting capacitance in high-performance computer systems","authors":"A. Chow, D. Hopkins, R. Drost, R. Ho","doi":"10.1109/VDAT.2008.4542411","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542411","url":null,"abstract":"Aggressive scaling of transistor feature sizes has enabled unprecedented levels of integration and corresponding performance improvements in VLSI systems. However, fabrication costs present barriers to continued growth in transistor density. Proximity Communication breaks these barriers by providing high-density, high-bandwidth, low-power, and scalable off-chip I/O, allowing designers to partition their designs into separate chips with significantly reduced performance penalties. This partitioning greatly improves chip and package yield, and enables modular assemblies of heterogeneous systems with customizable mixes of functional units tailored for specific end-user applications.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123292531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Transistor sizing and layout merging of basic cells in pass transistor logic cell library 通管逻辑单元库中基本单元的尺寸和布局合并
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542419
Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen
{"title":"Transistor sizing and layout merging of basic cells in pass transistor logic cell library","authors":"Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen","doi":"10.1109/VDAT.2008.4542419","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542419","url":null,"abstract":"In the past two decades, pass transistor logic has been shown to have smaller power and area cost compared to traditional CMOS logic for some applications. Some important issues related to the design of pass transistor cell library are discussed in this paper. First, the transistor sizing for the special inverter circuit in the cell library is addressed, which is quite different from the sizing of conventional CMOS inverter. Second, we create new cells that merge combinations of an inverters and some multiplexers in order to reduce the physical layout area. Experimental results show that the layout compaction method also reduces the delay and dynamic power. The proposed transistor sizing and layout compaction methods could be useful guidelines in designing the basic cells required in pass-transistor logic synthesis.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131487625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
New transient detection circuit for system-level ESD protection 新型系统级ESD暂态检测电路
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542442
Cheng-Cheng Yen, C. Liao, M. Ker
{"title":"New transient detection circuit for system-level ESD protection","authors":"Cheng-Cheng Yen, C. Liao, M. Ker","doi":"10.1109/VDAT.2008.4542442","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542442","url":null,"abstract":"A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-mum CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system- level ESD zapping.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134079378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A radix-4 soft-output Viterbi architecture 基数4软输出Viterbi架构
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542453
E. Haratsch, K. Fitzpatrick
{"title":"A radix-4 soft-output Viterbi architecture","authors":"E. Haratsch, K. Fitzpatrick","doi":"10.1109/VDAT.2008.4542453","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542453","url":null,"abstract":"A new radix-4 soft-output Viterbi architecture is presented, which achieves higher data rates than prior radix-2 SOVA designs. The proposed architecture is also more hardware-efficient than a previously reported radix-4 SOVA architecture. New circuits are presented for the generation of path metric differences, the path comparison unit, and reliability update unit. The presented architecture is suitable for highspeed applications such as magnetic recording, where data rates are currently approaching 3 Gb/s.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114619180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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