Transistor sizing and layout merging of basic cells in pass transistor logic cell library

Abstract

In the past two decades, pass transistor logic has been shown to have smaller power and area cost compared to traditional CMOS logic for some applications. Some important issues related to the design of pass transistor cell library are discussed in this paper. First, the transistor sizing for the special inverter circuit in the cell library is addressed, which is quite different from the sizing of conventional CMOS inverter. Second, we create new cells that merge combinations of an inverters and some multiplexers in order to reduce the physical layout area. Experimental results show that the layout compaction method also reduces the delay and dynamic power. The proposed transistor sizing and layout compaction methods could be useful guidelines in designing the basic cells required in pass-transistor logic synthesis.