基于0.13um CMOS技术的62-66.1GHz锁相环

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI:10.1109/VDAT.2008.4542425

Kun-Hung Tsai, Shen-Iuan Liu

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引用次数: 1

摘要

提出了一种基于0.13 um CMOS工艺的62-66.1 GHz锁相环。通过采用改进的大范围注入锁定分频器，所提出的锁相环显示了62至66.1 GHz的输出频率，允许在未经许可的60 GHz无线电中宽带应用。由于锁相环工作在66.09 GHz，在1 MHz偏移时测量到的相位噪声为-74.5 dBc/Hz。所提出的电路从1.5 V的电源电压中消耗89 mW的功率。

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A 62–66.1GHz phase-locked loop in 0.13um CMOS technology

This paper presents a 62-66.1 GHz phase-locked loop (PLL) in 0.13 um CMOS process. By employing a modified wide-range injection-locked frequency divider, the proposed PLL demonstrates the output frequency from 62 to 66.1 GHz which allowing wideband application in unlicensed 60 GHz radio. As the PLL operates at 66.09 GHz, the measured phase noise at 1 MHz offset is -74.5 dBc/Hz. The proposed circuit consumes a power of 89 mW from a 1.5 V supply voltage.

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2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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