基数4软输出Viterbi架构

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI:10.1109/VDAT.2008.4542453

E. Haratsch, K. Fitzpatrick

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引用次数: 1

摘要

提出了一种新的基数-4软输出Viterbi架构，该架构比以前的基数-2 SOVA设计实现了更高的数据速率。所建议的体系结构也比先前报道的基数4 SOVA体系结构具有更高的硬件效率。提出了路径度量差的生成电路、路径比较单元和可靠性更新单元。所提出的架构适用于高速应用，如磁记录，其中数据速率目前接近3gb /s。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A radix-4 soft-output Viterbi architecture

A new radix-4 soft-output Viterbi architecture is presented, which achieves higher data rates than prior radix-2 SOVA designs. The proposed architecture is also more hardware-efficient than a previously reported radix-4 SOVA architecture. New circuits are presented for the generation of path metric differences, the path comparison unit, and reliability update unit. The presented architecture is suitable for highspeed applications such as magnetic recording, where data rates are currently approaching 3 Gb/s.

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来源期刊

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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