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2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献

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A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus 一种用于低功耗片上总线的具有存储器的串扰避免码生成算法
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542440
Kuang-Chin Cheng, Jing-Yang Jou
{"title":"A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus","authors":"Kuang-Chin Cheng, Jing-Yang Jou","doi":"10.1109/VDAT.2008.4542440","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542440","url":null,"abstract":"In this paper, a bus encoding approach including related code generation algorithm for global data busses is developed to produce area-efficient crosstalk-avoidance (CA) codes with considering low-power requirements. Proposed codes are codes with memory using overlapping boundary strategy. The probabilistic distribution of input data could be included to reduce the power consumption. The performance improvement of CA codes is nearly 2times for heavily coupled busses based on theoretical analysis. As compared to uncoded data words, proposed codes show 12% to 38% energy- reduction on bus for an equi-probable 32-bit bus design.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131421736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 2.4-GHz 0.18-μm CMOS doubly balanced mixer with high linearity 2.4 ghz 0.18 μm CMOS双平衡高线性混频器
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542459
So-Yu Chao, Ching-Yuan Yang
{"title":"A 2.4-GHz 0.18-μm CMOS doubly balanced mixer with high linearity","authors":"So-Yu Chao, Ching-Yuan Yang","doi":"10.1109/VDAT.2008.4542459","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542459","url":null,"abstract":"A 2.4 GHz CMOS doubly balanced differential mixer with high linearity is presented in this paper. The differential mixer, fabricated with the 0.18 mum 1P6M CMOS process, uses direct-coupled strategy to increase linearity. The operating frequencies of RF, LO, and IF ports are 2.4 GHz, 2.25 GHz, and 150 MHz, respectively. The measured results of the proposed mixer exhibit 5.5 dB of conversion loss, +2 dBm of PldB compression point, +4.2 dBm of OIP3 and +9.2 dBm of IIP3 under a 4 dBm LO power and a 1.8 V supply voltage. The circuit dissipates 9 mW in the core and 9 mW in the output buffer. The chip area without pads is 0.014 mm2.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115348918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A novel miniaturized wide-band Wilkinson power divider employing two-dimensional transmission line 采用二维传输线的新型小型化宽带威尔金森功率分配器
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542450
Chih-Chiang Chen, J. Cin, Sheng-Huei Wang, Ching-Chyuan Lin, Ching-Kuang C. Tzuang
{"title":"A novel miniaturized wide-band Wilkinson power divider employing two-dimensional transmission line","authors":"Chih-Chiang Chen, J. Cin, Sheng-Huei Wang, Ching-Chyuan Lin, Ching-Kuang C. Tzuang","doi":"10.1109/VDAT.2008.4542450","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542450","url":null,"abstract":"The study proposes a novel miniaturized wide-band Wilkinson power divider, based on 0.18 mum 1P6M CMOS foundry technology. The proposed two-dimensional transmission line, called a complementary-conducting-strip (CCS), replaces the conventional microstrip (MS) line structure. With this CCS structure, the occupying area of this novel divider is approximately 96% smaller than that of the conventional MS Wilkinson power divider. The prototype, including the input/output (I/O) pads, occupies an area of only 673 mum by 645 mum. The new WPD has a coupling loss of -5.4 dB, an isolation of +15 dB and a return loss -12.5 dB from 8.7 GHz to 17.4 GHz.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115801126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A novel low-power processor with variable pipeline control 一种具有可变流水线控制的新型低功耗处理器
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542463
T. Shimada, T. Madokoro, H. Oshima, R. Kobayashi
{"title":"A novel low-power processor with variable pipeline control","authors":"T. Shimada, T. Madokoro, H. Oshima, R. Kobayashi","doi":"10.1109/VDAT.2008.4542463","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542463","url":null,"abstract":"One of the most attractive issues for microprocessors is low power design. So far there are many techniques has been used, but most of them are applied at the device level or at the circuit level. In this paper, we propose a novel technique applied at the architecture level. It reduces power consumption by controlling pipeline length. To attain arbitrary performance, we use proportional-integral control to adjust pipeline length and the control mechanism is implemented on-chip. The experimental results show that the mechanism can reduce power consumption by up to 14.1% and energy consumption by up to 23.0% compared with Dynamic Voltage and Frequency Scaling.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123302751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On minimizing topography variation in multi-layer oxide CMP manufacturability 最小化多层氧化物CMP可制造性中形貌变化的研究
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542407
Chi-Hui Shui, Hung-Ming Chen
{"title":"On minimizing topography variation in multi-layer oxide CMP manufacturability","authors":"Chi-Hui Shui, Hung-Ming Chen","doi":"10.1109/VDAT.2008.4542407","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542407","url":null,"abstract":"Due to advanced technology manufacturing variations, dummy metal insertion becomes the key process of VLSI fabrication in reducing wafer-topography variation in Al- based and Cu-based chemical mechanical polishing (CMP) processes. In this paper, we propose a faster and more effective approach to dealing with inter-layer dielectric (ILD) CMP issue, called Effective Model-based Dummy Insertion (EMDI). EMDI selects panels to insert dummy metal by effective CMP low pass filter model, and obtain feasible solutions with good quality based on minimized effective density. Compared with previous linear programming approach that costs 0(n3) (We have n * n panels in chip layout), EMDI is quite fast in O(nlogn) which is dominated by fast Fourier transformation. Multi-layer dummy metal insertion is considered in our framework as well. The experiments on a real design show that our approach has outperformed the previous approach, and is more efficient and effective in the smoothness of metal layers.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123634081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A self-testing and calibration technique for current-steering DACs 一种电流转向dac的自测试和校准技术
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542471
Yuan-Lang Ma, Jiun-Lang Huang
{"title":"A self-testing and calibration technique for current-steering DACs","authors":"Yuan-Lang Ma, Jiun-Lang Huang","doi":"10.1109/VDAT.2008.4542471","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542471","url":null,"abstract":"In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In self- testing mode, the controller executes the self-testing algorithm to characterize the DAC higher bits and computes the calibration information. In function mode, it produces the inputs to the duplicated lower bits for calibration. To validate the idea, a 14-bit prototype has been fabricated using TSMC 0.35 mum technology. The measurement results show that INL, DNL, and SFDR are significantly improved.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128637691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS low-noise amplifier with impedance feedback for ultra-wideband wireless receiver system 一种用于超宽带无线接收系统的阻抗反馈CMOS低噪声放大器
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542410
Zhe-Yang Huang, Che-Cheng Huang, Chun-Chieh Chen, C. Hung, C. Jou
{"title":"A CMOS low-noise amplifier with impedance feedback for ultra-wideband wireless receiver system","authors":"Zhe-Yang Huang, Che-Cheng Huang, Chun-Chieh Chen, C. Hung, C. Jou","doi":"10.1109/VDAT.2008.4542410","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542410","url":null,"abstract":"In this paper, a CMOS low-noise amplifier (LNA) is designed for ultra-wideband (UWB) wireless receiver system. The design consists of a wideband input impedance matching network, a cascoded amplifier with shunt-peaked load, a RLC-impedance feedback loop and an output buffer for measurement purpose. It is fabricated in TSMC 0.18 um standard RF CMOS process. The LNA gives 11.5 dB maximum power gain between 3.1 GHz-5.0 GHz while consuming 5.7 mW through a 1.8 V supply voltage. Over the 3.1 GHz-5.0 GHz frequency band, the minimum noise figure (NF) is 4.7 dB. Input return loss lower than -12.7 dB in all bandwidth have been achieved.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126500110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS 基于0.13um CMOS的1.6-880MHz可合成ADPLL
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542400
Hsiang-Hui Chang, Shang-Ming Lee, Chao-Wen Chou, Yu-Tung Chang, Yi-Li Cheng
{"title":"A 1.6–880MHz synthesizable ADPLL in 0.13um CMOS","authors":"Hsiang-Hui Chang, Shang-Ming Lee, Chao-Wen Chou, Yu-Tung Chang, Yi-Li Cheng","doi":"10.1109/VDAT.2008.4542400","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542400","url":null,"abstract":"A synthesizable all digital phase-locked loop (ADPLL) with an improved DCO and a frequency-bouncing-reduced algorithm is presented. The ADPLL covers 1.6-880 MHz frequency range while maintaining high frequency resolution. The synthesizable ADPLL can be easily migrated to different processes and foundries; requires less design time and maintain effort; and directly benefit from CMOS technology scaling. The PLL is fabricated in a 0.13-mum 1P6M high-Vt CMOS process and occupies an active area of 220 x 220 um2. The PLL consumes a maximum power of 16 mW and has 114 ps peak-to-peak jitter at 880 MHz.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121508813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 330MHz 11 bit 26.4mW CMOS low-hold-pedestal fully differential track-and-hold circuit 330MHz 11位26.4mW CMOS低保持座全差分跟踪保持电路
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258137
Tsung-Sum Lee, Chi-Chang Lu, Chih-chieh Ho
{"title":"A 330MHz 11 bit 26.4mW CMOS low-hold-pedestal fully differential track-and-hold circuit","authors":"Tsung-Sum Lee, Chi-Chang Lu, Chih-chieh Ho","doi":"10.1109/VDAT.2006.258137","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258137","url":null,"abstract":"A new technique for realizing a very-high-speed low-power low-voltage CMOS fully differential track-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switch. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detailed. A prototype circuit in a 0.35- mu m CMOS process is integrated and experimental results are presented.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123506348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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