A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus

Abstract

In this paper, a bus encoding approach including related code generation algorithm for global data busses is developed to produce area-efficient crosstalk-avoidance (CA) codes with considering low-power requirements. Proposed codes are codes with memory using overlapping boundary strategy. The probabilistic distribution of input data could be included to reduce the power consumption. The performance improvement of CA codes is nearly 2times for heavily coupled busses based on theoretical analysis. As compared to uncoded data words, proposed codes show 12% to 38% energy- reduction on bus for an equi-probable 32-bit bus design.