{"title":"一种电流转向dac的自测试和校准技术","authors":"Yuan-Lang Ma, Jiun-Lang Huang","doi":"10.1109/VDAT.2008.4542471","DOIUrl":null,"url":null,"abstract":"In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In self- testing mode, the controller executes the self-testing algorithm to characterize the DAC higher bits and computes the calibration information. In function mode, it produces the inputs to the duplicated lower bits for calibration. To validate the idea, a 14-bit prototype has been fabricated using TSMC 0.35 mum technology. The measurement results show that INL, DNL, and SFDR are significantly improved.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A self-testing and calibration technique for current-steering DACs\",\"authors\":\"Yuan-Lang Ma, Jiun-Lang Huang\",\"doi\":\"10.1109/VDAT.2008.4542471\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In self- testing mode, the controller executes the self-testing algorithm to characterize the DAC higher bits and computes the calibration information. In function mode, it produces the inputs to the duplicated lower bits for calibration. To validate the idea, a 14-bit prototype has been fabricated using TSMC 0.35 mum technology. The measurement results show that INL, DNL, and SFDR are significantly improved.\",\"PeriodicalId\":156790,\"journal\":{\"name\":\"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2008.4542471\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542471","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A self-testing and calibration technique for current-steering DACs
In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In self- testing mode, the controller executes the self-testing algorithm to characterize the DAC higher bits and computes the calibration information. In function mode, it produces the inputs to the duplicated lower bits for calibration. To validate the idea, a 14-bit prototype has been fabricated using TSMC 0.35 mum technology. The measurement results show that INL, DNL, and SFDR are significantly improved.
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