{"title":"A 2.4-GHz 0.18-μm CMOS doubly balanced mixer with high linearity","authors":"So-Yu Chao, Ching-Yuan Yang","doi":"10.1109/VDAT.2008.4542459","DOIUrl":null,"url":null,"abstract":"A 2.4 GHz CMOS doubly balanced differential mixer with high linearity is presented in this paper. The differential mixer, fabricated with the 0.18 mum 1P6M CMOS process, uses direct-coupled strategy to increase linearity. The operating frequencies of RF, LO, and IF ports are 2.4 GHz, 2.25 GHz, and 150 MHz, respectively. The measured results of the proposed mixer exhibit 5.5 dB of conversion loss, +2 dBm of PldB compression point, +4.2 dBm of OIP3 and +9.2 dBm of IIP3 under a 4 dBm LO power and a 1.8 V supply voltage. The circuit dissipates 9 mW in the core and 9 mW in the output buffer. The chip area without pads is 0.014 mm2.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542459","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A 2.4 GHz CMOS doubly balanced differential mixer with high linearity is presented in this paper. The differential mixer, fabricated with the 0.18 mum 1P6M CMOS process, uses direct-coupled strategy to increase linearity. The operating frequencies of RF, LO, and IF ports are 2.4 GHz, 2.25 GHz, and 150 MHz, respectively. The measured results of the proposed mixer exhibit 5.5 dB of conversion loss, +2 dBm of PldB compression point, +4.2 dBm of OIP3 and +9.2 dBm of IIP3 under a 4 dBm LO power and a 1.8 V supply voltage. The circuit dissipates 9 mW in the core and 9 mW in the output buffer. The chip area without pads is 0.014 mm2.