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A 10-bit 300MHz 0.1mm2 triple-channel current-steering DAC 75.98dB SFDR in 65nm 一个10位300MHz 0.1mm2三通道电流转向DAC在65nm 75.98dB SFDR
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542434
G.M. Hong, Shih-Hsuan Hsu, Yan-Hua Peng, A. Chen, Yi-Ti Wang, Hsin-Hung Lu
{"title":"A 10-bit 300MHz 0.1mm2 triple-channel current-steering DAC 75.98dB SFDR in 65nm","authors":"G.M. Hong, Shih-Hsuan Hsu, Yan-Hua Peng, A. Chen, Yi-Ti Wang, Hsin-Hung Lu","doi":"10.1109/VDAT.2008.4542434","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542434","url":null,"abstract":"For this paper, we used the UMC 65 nm 1P10M CMOS logic process to design a 10-bit triple-channel current- steering DAC, which includes three channels of RGB. The analog/digital circuit was 2.5 V/1.2 V, the active area was 0.1 mm2 per channel, and INL/DNL were each less than plusmn 0.4/plusmn 0.23LSB. We obtained an SFDR exceeding 75.98 dB while consuming only 6.24 mW of power per channel.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131610636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 300MHz, 48mW analog front-end design for IEEE 802.3an 10GBase-T Ethernet 300MHz, 48mW模拟前端设计，用于IEEE 802.3an 10GBase-T以太网
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542435
Kai-Hsiang Chuang, J. Yeh, Chao-Shiun Wang, Chorng-Kuang Wang
{"title":"A 300MHz, 48mW analog front-end design for IEEE 802.3an 10GBase-T Ethernet","authors":"Kai-Hsiang Chuang, J. Yeh, Chao-Shiun Wang, Chorng-Kuang Wang","doi":"10.1109/VDAT.2008.4542435","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542435","url":null,"abstract":"This paper presents a receiver analog front-end (AFE) for 10GBase-T Ethernet system. The AFE can provide 14 dB voltage gain with 9 dB gain control range, and the gain step is 1.5 dB with +/-0.25 dB gain error. The analog front-end -3 dB bandwidth is 300 MHz. The 3rd harmonic distortion (HD3) is lower than -50 dB. It consumes 48 mW for 1.8 V supply voltage. This AFE is fabricated in 0.18-mum 1P6M CMOS technology and the chip area is 0.88times0.82 mm2.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122105660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 120-MHz active-RC filter with an agile frequency tuning scheme in 0.18-μm CMOS 基于0.18 μm CMOS的120 mhz有源rc滤波器
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542449
Yu-Chih Chen, W. Chiu, Tsung-Hsien Lin
{"title":"A 120-MHz active-RC filter with an agile frequency tuning scheme in 0.18-μm CMOS","authors":"Yu-Chih Chen, W. Chiu, Tsung-Hsien Lin","doi":"10.1109/VDAT.2008.4542449","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542449","url":null,"abstract":"A wideband active-RC low-pass filter realized for high data rate wireless receivers is reported in this paper. This filter adopts the 5th-order elliptic topology and achieves a bandwidth of 120 MHz and a stopband attenuation of more than 45 dB. The wide-bandwidth operational amplifiers employed in the filter adopt the feedforward compensation technique to extend the unity-gain bandwidth to 4.1 GHz. An agile tuning scheme is also proposed to automatically adjust the filter cutoff frequency. It uses the successive approximation register counter in the digital tuning loop to compensate for the RC variations while achieves short calibration time. The filter is fabricated in the TSMC 0.18-mum CMOS process and dissipates 38 mW under 1.5-V supply voltage. The measured IIP3 is 21 dBm and the tuning time is 8 mus.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116794537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Estimation of energy consumed by software in processor caches 估计软件在处理器缓存中消耗的能量
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542403
L. Chandra, Sourav Roy
{"title":"Estimation of energy consumed by software in processor caches","authors":"L. Chandra, Sourav Roy","doi":"10.1109/VDAT.2008.4542403","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542403","url":null,"abstract":"We present a comprehensive high-level estimation framework for power consumed by the software in the processor caches. We demonstrate the framework on two types of caches commonly used in a modern day processor ARM1136 viz., L1 Data Cache and L2 Unified Cache. The major contribution of this paper is a linear energy model for the caches. The energy characterization starts with recognition of different types of operations in the caches. Further the energy of each operation is divided into sequential and non-sequential part depending on whether the operation is stand alone or happens in a burst with other operations. There is also an idle energy component of the cache since the cache may be inactive for considerable amount of time. The average error magnitude of the energy model when applied on the ARM1136 L1 Data Cache and L2 Unified Cache with a large suite of benchmarks is 1.7%, whereas the maximum error is less than 4.0%.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115139074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High-level synthesis algorithms with floorplaning for distributed/shared-register architectures 面向分布式/共享寄存器体系结构的高级综合算法
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542438
A. Ohchi, N. Togawa, M. Yanagisawa, T. Ohtsuki
{"title":"High-level synthesis algorithms with floorplaning for distributed/shared-register architectures","authors":"A. Ohchi, N. Togawa, M. Yanagisawa, T. Ohtsuki","doi":"10.1109/VDAT.2008.4542438","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542438","url":null,"abstract":"In this paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back floorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126238647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Obstacle-Avoiding Rectilinear Steiner Minimal Tree construction 避障直线Steiner最小树构造
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542406
Y. Chang, Y. Tsai, J. Chi, Mely Chen Chi
{"title":"Obstacle-Avoiding Rectilinear Steiner Minimal Tree construction","authors":"Y. Chang, Y. Tsai, J. Chi, Mely Chen Chi","doi":"10.1109/VDAT.2008.4542406","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542406","url":null,"abstract":"We present a construction-by-correction approach to solve the obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction problem. We build an obstacle-weighted spanning tree as a guidance to construct OARSMT on an escape graph. We use Dijkstra's algorithm for routing. A refinement of U- shaped removal is applied during the routing process to further reduce the wire length. Our experimental results show that comparing to several state-of-the-art works this algorithm achieves the shortest average total wire length. It also uses short run time for practical-size problems.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123234150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A transceiver 10GBase-T in 90nm CMOS 收发器10GBase-T在90nm CMOS
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542399
Kai-Yin Liu, Yi-Kuang Chen, Chen-Chih Huang, Chao-Cheng Lee, Leon Lin, J. Chou
{"title":"A transceiver 10GBase-T in 90nm CMOS","authors":"Kai-Yin Liu, Yi-Kuang Chen, Chen-Chih Huang, Chao-Cheng Lee, Leon Lin, J. Chou","doi":"10.1109/VDAT.2008.4542399","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542399","url":null,"abstract":"This work presents a single channel (cable) prototype lOGBase-T transceiver fabricated in a 90nm CMOS process. A 1.2V/3.3V dual supply is used. The transmitter, consuming 93.7mW, features a class- AB line driver using an AC coupled bias and a common-mode (CM) compensation capacitor transparent to the differential-mode (DM) path to achieve high efficiency. It achieves 59.51dB SFDR for a test signal at 30MHz. The receiver, consuming 24mW, features a PGA using a two-stage cascode Miller compensated op-amp and a multiple feedback low-pass filter. It achieves 59.7dB SFDR for a test signal at 100MHz. The total chip area is 1.7*1.36 mm2.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116555681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Technology trend of ADCs adc的技术趋势
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542441
A. Matsuzawa
{"title":"Technology trend of ADCs","authors":"A. Matsuzawa","doi":"10.1109/VDAT.2008.4542441","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542441","url":null,"abstract":"This paper discusses technology trend of ADCs. Technology scaling has enabled an increased conversion rate; however, it now also leads to difficulties to increase or to maintain performance of ADCs. New converter design challenges have been started. One strong trend in design of ADCs is to omit operational amplifiers (OpAmps), which used to form the basis of modern ADC design but are now no longer useful. Comparator base ADCs, such as successive approximation ADCs become very attractive in future energy efficient and scaled CMOS conscious ADC architectures.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133361269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics 8.69 Mvertices/s 2.78 Mpixels/s基于tile的3d图形全流水线，具有嵌入式性能计数模块，实时总线跟踪器和协议检查器，适用于消费电子产品
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542412
Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Chung-Hua Tsai, Tzu-Ching Tien, Da-Jing Zhang-Jian, Sheng-Yu Chiu, Ing-Jer Huang, Yun-Nan Chang, Shen-Fu Hsiao, Jin-Hua Hong, Chung-Nan Lee, Ming-Chao Chiang
{"title":"An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics","authors":"Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Chung-Hua Tsai, Tzu-Ching Tien, Da-Jing Zhang-Jian, Sheng-Yu Chiu, Ing-Jer Huang, Yun-Nan Chang, Shen-Fu Hsiao, Jin-Hua Hong, Chung-Nan Lee, Ming-Chao Chiang","doi":"10.1109/VDAT.2008.4542412","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542412","url":null,"abstract":"A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm2. The IP includes embedded circuitry to monitor run time 3DG characteristics, detect bus protocol error and inefficiency, and capture bus trace at various abstraction levels with compression ratio up to 98%.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125192871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multilevel communication modeling for Multiprocessor System-on-Chip 多处理器片上系统的多级通信建模
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542431
K. Popovici, A. Jerraya
{"title":"Multilevel communication modeling for Multiprocessor System-on-Chip","authors":"K. Popovici, A. Jerraya","doi":"10.1109/VDAT.2008.4542431","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542431","url":null,"abstract":"The high complexity of current multi-processor system on chip (MPSoC) impels the designers to model and simulate the system components and their interaction in the early design stages. High level modeling usually requires less modeling effort and executes faster. In this paper we propose high level communication models that allow early MPSoC design, performance estimation and evaluation of the application's communication requirements. We applied the proposed modeling methods to analyze the impact on performance for different communication architectures for the H.264 Encoder running on a complex MPSoC platform.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133801681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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