2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)最新文献_第6页

A universal look-ahead algorithm for pipelining IIR filters 流水线IIR滤波器的通用预查算法

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542462

Yen-Liang Chen, Chun-Yu Chen, Kai-Yuan Jheng, A. Wu

引用次数: 7

High-throughput 12-mode CTC decoder for WiMAX standard 用于WiMAX标准的高吞吐量12模式CTC解码器

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542451

Cheng-Hung Lin, Chun-Yu Chen, A. Wu

引用次数: 20

A 1.1-V CMOS frequency synthesizer with pass-transistor-logic prescaler for U-NII band system 一种用于U-NII波段系统的1.1 v CMOS频率合成器，带通管逻辑预分频器

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542426

Jia-Lung Cheng, Chao-Shiun Wang, Wei-Chang Li, Chorng-Kuang Wang

引用次数: 1

Design of an OFDMA baseband receiver for 3GPP long-term evolution 面向3GPP长期演进的OFDMA基带接收机设计

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542446

Chin-Wei Chu, Chia-Ching Lee, Yuan-Hao Huang

引用次数: 5

A hardware/software co-solution to achieving high throughput required by motion estimation part in H.264/AVC HDTV real-time application 为实现H.264/AVC高清电视实时应用中运动估计部分所需的高吞吐量，提出了一种软硬件协同解决方案

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542429

Zhenxing Chen, T. Ikenaga, S. Goto

{"title":"A hardware/software co-solution to achieving high throughput required by motion estimation part in H.264/AVC HDTV real-time application","authors":"Zhenxing Chen, T. Ikenaga, S. Goto","doi":"10.1109/VDAT.2008.4542429","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542429","url":null,"abstract":"The high throughput required by Motion Estimation (ME) part in H.264/AVC High Definition TV (HDTV) real-time application is very difficult to achieve. Currently one kind of the solutions to this problem is multipling the processing element (PE) array to construct redundant PE array structure. Although redundant structure can take advantages of parallel processing to achieve high throughput, meanwhile it bring in linear increasing of hardware cost. In this paper, a hardware/software co-solusion is proposed to achieve the required throughput of ME part in H.264/AVC HDTV realtime application. In software side, one adaptive search range (ASR) algorithm which is previously proposed by us [12] is firstly introduced and then experimentally proved can improve the throughput 11.48 times averagely in HDTV1080p video sequence. In hardware side, a previously proposed architecture called SAD-tree [17] is firstly introduced. Then based on this architecture, optimization that increase the frequence is proposed. The hardware implementing result of the optimized architecture shows the proposed optimization can triple the frequence. Finally, it is illustrated that the hardware/software co-solution can help to achieve the required throughput.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125556777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Impact quantification of the dummy metal fills on nanometer VLSI designs for DFM 虚拟金属填充对DFM纳米VLSI设计的影响量化

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542470

Keh-Jeng Chang, Jyh-Jeng Chou, Hung-Chih Li, Kuo-Cheng Chang

引用次数: 2

A 0.35-um CMOS switched-inductor dual-band LC-tank frequency divider 一个0.35微米CMOS开关电感双带LC-tank分频器

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542457

S. Jang, Che Yi Lin, Chien-Feng Lee

引用次数: 8

A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing 一种节能的SRAM核心架构，具有无分割和矩形可访问性，用于超并行视频处理

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542413

Y. Murachi, T. Kamino, J. Miyakoshi, H. Kawaguchi, M. Yoshimoto

引用次数: 10

Adaptive digital techniques for efficiency and linearity enhancement of CMOS RF power amplifiers 提高CMOS射频功率放大器效率和线性度的自适应数字技术

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542443

D. Kwon, Hao Li, Y. Chili

引用次数: 3

A systematic methodology to employ error-tolerance for yield improvement 一种采用容错来提高成品率的系统方法

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI: 10.1109/VDAT.2008.4542423

Tong-Yu Hsieh, Kuen-Jong Lee, Chia-Lin Lu, M. Breuer

{"title":"A systematic methodology to employ error-tolerance for yield improvement","authors":"Tong-Yu Hsieh, Kuen-Jong Lee, Chia-Lin Lu, M. Breuer","doi":"10.1109/VDAT.2008.4542423","DOIUrl":"https://doi.org/10.1109/VDAT.2008.4542423","url":null,"abstract":"Error-tolerance is an innovative concept that can significantly improve the yield of integrated circuits (IC's) by identifying defective yet acceptable chips. A systematic method to employ this concept, however, has not been addressed. In this paper, we propose a general methodology to systematically utilize error- tolerance for practical applications. The proposed methodology explores the error-tolerance features of target designs, evaluates the acceptability of defective chips, and predicts the yield improvement that can be achieved. To illustrate and validate the proposed methodology, we employ a discrete cosine transform (DCT) circuit that has been widely used in multimedia compression systems in a case study. By applying the proposed methodology to the DCT, an error-tolerant design flow is established. Proper attributes are determined for acceptability evaluation, and corresponding test methods are developed to identify acceptable chips. Experimental results show that one can easily specify various acceptability thresholds of the identified error-tolerable attributes to obtain different degrees of yield improvement, which validates the efficiency and effectiveness of the proposed methodology.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122448256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0