Jia-Lung Cheng, Chao-Shiun Wang, Wei-Chang Li, Chorng-Kuang Wang
{"title":"A 1.1-V CMOS frequency synthesizer with pass-transistor-logic prescaler for U-NII band system","authors":"Jia-Lung Cheng, Chao-Shiun Wang, Wei-Chang Li, Chorng-Kuang Wang","doi":"10.1109/VDAT.2008.4542426","DOIUrl":null,"url":null,"abstract":"This paper presents a 1.1-V low-voltage frequency synthesizer for U-NII band system. In order to achieve low-voltage and high-speed operations, a new 32/33 dual-modulus prescaler with pass-transistor-logic (PTL) topology and folding-injection architecture is proposed. Fabricated in 0.18-mum CMOS technology, the measured phase noise of the 6.08-GHz frequency synthesizer at a 1 MHz offset is -114 dBc/Hz and the reference spur at an offset of 5 MHz is less than 61 dBc. The settling time within 20 ppm after 640 MHz jump (widest jump from low band to high band) is less than 40 mus. The frequency synthesizer dissipates 31 mW from a 1.1-V supply and occupies a chip area of 1.3 mm2.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542426","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a 1.1-V low-voltage frequency synthesizer for U-NII band system. In order to achieve low-voltage and high-speed operations, a new 32/33 dual-modulus prescaler with pass-transistor-logic (PTL) topology and folding-injection architecture is proposed. Fabricated in 0.18-mum CMOS technology, the measured phase noise of the 6.08-GHz frequency synthesizer at a 1 MHz offset is -114 dBc/Hz and the reference spur at an offset of 5 MHz is less than 61 dBc. The settling time within 20 ppm after 640 MHz jump (widest jump from low band to high band) is less than 40 mus. The frequency synthesizer dissipates 31 mW from a 1.1-V supply and occupies a chip area of 1.3 mm2.