{"title":"Design of an OFDMA baseband receiver for 3GPP long-term evolution","authors":"Chin-Wei Chu, Chia-Ching Lee, Yuan-Hao Huang","doi":"10.1109/VDAT.2008.4542446","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a downlink OFDMA processor based on the 3GPP LTE. This processor supports scalable bandwidth for different OFDMA modes. A low-cost sampling rate conversion is employed to obtain different sampling rates for different bandwidths. Timing and frequency synchronization are then designed to recover the time and frequency mismatch between the transmitter and receiver. Afterward, sampling clock offset is tracked and compensated in the frequency domain. Finally, reconfigurable channel estimation and equalization are designed for optimal performance. The circuit architecture is designed and simulated to show that its performance meets the system requirement.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542446","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this paper, we propose a downlink OFDMA processor based on the 3GPP LTE. This processor supports scalable bandwidth for different OFDMA modes. A low-cost sampling rate conversion is employed to obtain different sampling rates for different bandwidths. Timing and frequency synchronization are then designed to recover the time and frequency mismatch between the transmitter and receiver. Afterward, sampling clock offset is tracked and compensated in the frequency domain. Finally, reconfigurable channel estimation and equalization are designed for optimal performance. The circuit architecture is designed and simulated to show that its performance meets the system requirement.