一种用于U-NII波段系统的1.1 v CMOS频率合成器,带通管逻辑预分频器

Jia-Lung Cheng, Chao-Shiun Wang, Wei-Chang Li, Chorng-Kuang Wang
{"title":"一种用于U-NII波段系统的1.1 v CMOS频率合成器,带通管逻辑预分频器","authors":"Jia-Lung Cheng, Chao-Shiun Wang, Wei-Chang Li, Chorng-Kuang Wang","doi":"10.1109/VDAT.2008.4542426","DOIUrl":null,"url":null,"abstract":"This paper presents a 1.1-V low-voltage frequency synthesizer for U-NII band system. In order to achieve low-voltage and high-speed operations, a new 32/33 dual-modulus prescaler with pass-transistor-logic (PTL) topology and folding-injection architecture is proposed. Fabricated in 0.18-mum CMOS technology, the measured phase noise of the 6.08-GHz frequency synthesizer at a 1 MHz offset is -114 dBc/Hz and the reference spur at an offset of 5 MHz is less than 61 dBc. The settling time within 20 ppm after 640 MHz jump (widest jump from low band to high band) is less than 40 mus. The frequency synthesizer dissipates 31 mW from a 1.1-V supply and occupies a chip area of 1.3 mm2.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 1.1-V CMOS frequency synthesizer with pass-transistor-logic prescaler for U-NII band system\",\"authors\":\"Jia-Lung Cheng, Chao-Shiun Wang, Wei-Chang Li, Chorng-Kuang Wang\",\"doi\":\"10.1109/VDAT.2008.4542426\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 1.1-V low-voltage frequency synthesizer for U-NII band system. In order to achieve low-voltage and high-speed operations, a new 32/33 dual-modulus prescaler with pass-transistor-logic (PTL) topology and folding-injection architecture is proposed. Fabricated in 0.18-mum CMOS technology, the measured phase noise of the 6.08-GHz frequency synthesizer at a 1 MHz offset is -114 dBc/Hz and the reference spur at an offset of 5 MHz is less than 61 dBc. The settling time within 20 ppm after 640 MHz jump (widest jump from low band to high band) is less than 40 mus. The frequency synthesizer dissipates 31 mW from a 1.1-V supply and occupies a chip area of 1.3 mm2.\",\"PeriodicalId\":156790,\"journal\":{\"name\":\"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2008.4542426\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542426","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

本文介绍了一种用于U-NII频段系统的1.1 v低压频率合成器。为了实现低电压和高速运算,提出了一种新型的32/33双模预分频器,具有通管逻辑(PTL)拓扑结构和折叠注入结构。采用0.18 μ m CMOS工艺制作的6.08 ghz频率合成器在1 MHz偏置时的相位噪声测量值为-114 dBc/Hz,在5 MHz偏置时的参考杂散小于61 dBc。640mhz跳变(从低频段到高频段的最宽跳变)后20 ppm内的沉降时间小于40 mus。频率合成器从1.1 v电源耗散31 mW,占用1.3 mm2的芯片面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 1.1-V CMOS frequency synthesizer with pass-transistor-logic prescaler for U-NII band system
This paper presents a 1.1-V low-voltage frequency synthesizer for U-NII band system. In order to achieve low-voltage and high-speed operations, a new 32/33 dual-modulus prescaler with pass-transistor-logic (PTL) topology and folding-injection architecture is proposed. Fabricated in 0.18-mum CMOS technology, the measured phase noise of the 6.08-GHz frequency synthesizer at a 1 MHz offset is -114 dBc/Hz and the reference spur at an offset of 5 MHz is less than 61 dBc. The settling time within 20 ppm after 640 MHz jump (widest jump from low band to high band) is less than 40 mus. The frequency synthesizer dissipates 31 mW from a 1.1-V supply and occupies a chip area of 1.3 mm2.
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