A power-efficient SRAM core architecture with segmentation-free and rectangular accessibility for super-parallel video processing

Abstract

This paper describes a unique SRAM architecture for super- parallel video processing. It features one cycle functional access of a rectangular image data (n x m pixels) with segmentation-free. To achieve this accessibility, a local word-line select scheme and a merged X-decoder method are newly introduced with elimination of extra X-decoder employed in usage of the conventional divided SRAM macro. The proposed SRAM has been adopted to a search window buffer for H.264 motion estimation processor for HDTV resolution video. As a result, a power and area of the search window buffer are reduced by 49% and by 48%, respectively. Furthermore, it is shown that the proposed SRAM is more efficient for super-HDTV resolution video which requires more parallelism.