收发器10GBase-T在90nm CMOS

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI:10.1109/VDAT.2008.4542399

Kai-Yin Liu, Yi-Kuang Chen, Chen-Chih Huang, Chao-Cheng Lee, Leon Lin, J. Chou

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引用次数: 1

摘要

这项工作提出了一个用90nm CMOS工艺制造的单通道(电缆)lOGBase-T收发器原型。采用1.2V/3.3V双电源。该发射机功耗为93.7mW，采用AB类线路驱动器，采用交流耦合偏置和对差模(DM)路径透明的共模(CM)补偿电容，以实现高效率。在30MHz的测试信号下，SFDR达到59.51dB。该接收器功耗为24mW，采用PGA，采用两级级联码米勒补偿运算放大器和多反馈低通滤波器。在100MHz的测试信号下，SFDR达到59.7dB。总芯片面积为1.7*1.36 mm2。

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A transceiver 10GBase-T in 90nm CMOS

This work presents a single channel (cable) prototype lOGBase-T transceiver fabricated in a 90nm CMOS process. A 1.2V/3.3V dual supply is used. The transmitter, consuming 93.7mW, features a class- AB line driver using an AC coupled bias and a common-mode (CM) compensation capacitor transparent to the differential-mode (DM) path to achieve high efficiency. It achieves 59.51dB SFDR for a test signal at 30MHz. The receiver, consuming 24mW, features a PGA using a two-stage cascode Miller compensated op-amp and a multiple feedback low-pass filter. It achieves 59.7dB SFDR for a test signal at 100MHz. The total chip area is 1.7*1.36 mm2.

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来源期刊

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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