{"title":"8.69 Mvertices/s 2.78 Mpixels/s基于tile的3d图形全流水线，具有嵌入式性能计数模块，实时总线跟踪器和协议检查器，适用于消费电子产品","authors":"Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Chung-Hua Tsai, Tzu-Ching Tien, Da-Jing Zhang-Jian, Sheng-Yu Chiu, Ing-Jer Huang, Yun-Nan Chang, Shen-Fu Hsiao, Jin-Hua Hong, Chung-Nan Lee, Ming-Chao Chiang","doi":"10.1109/VDAT.2008.4542412","DOIUrl":null,"url":null,"abstract":"A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm2. The IP includes embedded circuitry to monitor run time 3DG characteristics, detect bus protocol error and inefficiency, and capture bus trace at various abstraction levels with compression ratio up to 98%.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics\",\"authors\":\"Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Chung-Hua Tsai, Tzu-Ching Tien, Da-Jing Zhang-Jian, Sheng-Yu Chiu, Ing-Jer Huang, Yun-Nan Chang, Shen-Fu Hsiao, Jin-Hua Hong, Chung-Nan Lee, Ming-Chao Chiang\",\"doi\":\"10.1109/VDAT.2008.4542412\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm2. The IP includes embedded circuitry to monitor run time 3DG characteristics, detect bus protocol error and inefficiency, and capture bus trace at various abstraction levels with compression ratio up to 98%.\",\"PeriodicalId\":156790,\"journal\":{\"name\":\"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2008.4542412\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542412","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
一个基于平铺的3D图形IP被设计为支持OpenGL ES 1.0。测试芯片运行频率为139mhz，芯片尺寸为15.7 mm2，实现8.69 Mvertices/s和278 Mpixels/s。IP包括嵌入式电路，用于监控运行时3DG特性，检测总线协议错误和低效率，并以高达98%的压缩比捕获各种抽象级别的总线跟踪。
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics
A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm2. The IP includes embedded circuitry to monitor run time 3DG characteristics, detect bus protocol error and inefficiency, and capture bus trace at various abstraction levels with compression ratio up to 98%.
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