300MHz, 48mW模拟前端设计，用于IEEE 802.3an 10GBase-T以太网

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI:10.1109/VDAT.2008.4542435

Kai-Hsiang Chuang, J. Yeh, Chao-Shiun Wang, Chorng-Kuang Wang

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引用次数: 1

摘要

本文介绍了一种用于10GBase-T以太网系统的接收机模拟前端(AFE)。该AFE可提供14 dB的电压增益，增益控制范围为9 dB，增益步长为1.5 dB，增益误差为+/-0.25 dB。模拟前端- 3db带宽为300mhz。三次谐波失真(HD3)低于- 50db。在1.8 V电源电压下消耗48mw。该AFE采用0.18 μ m 1P6M CMOS技术制造，芯片面积为0.88 × 0.82 mm2。

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A 300MHz, 48mW analog front-end design for IEEE 802.3an 10GBase-T Ethernet

This paper presents a receiver analog front-end (AFE) for 10GBase-T Ethernet system. The AFE can provide 14 dB voltage gain with 9 dB gain control range, and the gain step is 1.5 dB with +/-0.25 dB gain error. The analog front-end -3 dB bandwidth is 300 MHz. The 3rd harmonic distortion (HD3) is lower than -50 dB. It consumes 48 mW for 1.8 V supply voltage. This AFE is fabricated in 0.18-mum 1P6M CMOS technology and the chip area is 0.88times0.82 mm2.

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2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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