Multilevel communication modeling for Multiprocessor System-on-Chip

Abstract

The high complexity of current multi-processor system on chip (MPSoC) impels the designers to model and simulate the system components and their interaction in the early design stages. High level modeling usually requires less modeling effort and executes faster. In this paper we propose high level communication models that allow early MPSoC design, performance estimation and evaluation of the application's communication requirements. We applied the proposed modeling methods to analyze the impact on performance for different communication architectures for the H.264 Encoder running on a complex MPSoC platform.