A 330MHz 11 bit 26.4mW CMOS low-hold-pedestal fully differential track-and-hold circuit

A new technique for realizing a very-high-speed low-power low-voltage CMOS fully differential track-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switch. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detailed. A prototype circuit in a 0.35- mu m CMOS process is integrated and experimental results are presented.