A novel low-power processor with variable pipeline control

Abstract

One of the most attractive issues for microprocessors is low power design. So far there are many techniques has been used, but most of them are applied at the device level or at the circuit level. In this paper, we propose a novel technique applied at the architecture level. It reduces power consumption by controlling pipeline length. To attain arbitrary performance, we use proportional-integral control to adjust pipeline length and the control mechanism is implemented on-chip. The experimental results show that the mechanism can reduce power consumption by up to 14.1% and energy consumption by up to 23.0% compared with Dynamic Voltage and Frequency Scaling.