{"title":"New transient detection circuit for system-level ESD protection","authors":"Cheng-Cheng Yen, C. Liao, M. Ker","doi":"10.1109/VDAT.2008.4542442","DOIUrl":null,"url":null,"abstract":"A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-mum CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system- level ESD zapping.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542442","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-mum CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system- level ESD zapping.
提出了一种用于系统级静电放电保护的片上瞬态检测电路。通过包含这种新的片上瞬态检测电路,可以共同设计硬件/固件解决方案与上电复位电路合作,以解决系统级ESD问题。利用HSPICE仿真器研究了该电路检测不同正负电瞬变的性能,并在硅片上进行了验证。在0.18 μ m CMOS工艺上的实验结果表明,所提出的片上瞬态检测电路能够检测到系统级ESD冲击过程中的快速电瞬态。