{"title":"Exploiting capacitance in high-performance computer systems","authors":"A. Chow, D. Hopkins, R. Drost, R. Ho","doi":"10.1109/VDAT.2008.4542411","DOIUrl":null,"url":null,"abstract":"Aggressive scaling of transistor feature sizes has enabled unprecedented levels of integration and corresponding performance improvements in VLSI systems. However, fabrication costs present barriers to continued growth in transistor density. Proximity Communication breaks these barriers by providing high-density, high-bandwidth, low-power, and scalable off-chip I/O, allowing designers to partition their designs into separate chips with significantly reduced performance penalties. This partitioning greatly improves chip and package yield, and enables modular assemblies of heterogeneous systems with customizable mixes of functional units tailored for specific end-user applications.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542411","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Aggressive scaling of transistor feature sizes has enabled unprecedented levels of integration and corresponding performance improvements in VLSI systems. However, fabrication costs present barriers to continued growth in transistor density. Proximity Communication breaks these barriers by providing high-density, high-bandwidth, low-power, and scalable off-chip I/O, allowing designers to partition their designs into separate chips with significantly reduced performance penalties. This partitioning greatly improves chip and package yield, and enables modular assemblies of heterogeneous systems with customizable mixes of functional units tailored for specific end-user applications.