{"title":"克服高速电路工艺变化的自适应偏置电路","authors":"Luis Chen, C. Yue","doi":"10.1109/VDAT.2008.4542458","DOIUrl":null,"url":null,"abstract":"A self-biased, VTH tracking current reference circuit is designed in 90 nm CMOS process. A finite state machine automatically adjusts the reference current to achieve plusmn5% deviation across process variation. The bias circuit is used on a differential test circuit and simulation shows a maximum of 8.53% variation in bias current.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology\",\"authors\":\"Luis Chen, C. Yue\",\"doi\":\"10.1109/VDAT.2008.4542458\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A self-biased, VTH tracking current reference circuit is designed in 90 nm CMOS process. A finite state machine automatically adjusts the reference current to achieve plusmn5% deviation across process variation. The bias circuit is used on a differential test circuit and simulation shows a maximum of 8.53% variation in bias current.\",\"PeriodicalId\":156790,\"journal\":{\"name\":\"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2008.4542458\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542458","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Adaptive biasing circuit overcoming process variation for high-speed circuits in scaled CMOS technology
A self-biased, VTH tracking current reference circuit is designed in 90 nm CMOS process. A finite state machine automatically adjusts the reference current to achieve plusmn5% deviation across process variation. The bias circuit is used on a differential test circuit and simulation shows a maximum of 8.53% variation in bias current.