1-GS/s CMOS 6位闪存ADC与偏移校准方法

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI:10.1109/VDAT.2008.4542455

C. Chang, Chih-Yi Hsiao, Ching-Yuan Yang

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引用次数: 10

摘要

本文设计了一个1-GS/s的6位闪存型模数转换器(ADC)。为了提高ADC的性能，采用了偏置校准方法。为了减小模数转换器的输入电容和校准电路的数量，采用了有源插值技术。测量结果表明，在1 GS/s频率下，该ADC在7 MHz输入时的信噪比为32.5 dB，在108 MHz输入时的信噪比为25.4 dB。功率消耗为550mw在1 GS/s从1.8 v电源。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 1-GS/s CMOS 6-bit flash ADC with an offset calibrating method

In this paper a 1-GS/s 6-bit flash type analog-to-digital converter (ADC) is designed in 0.18-mum one-poly six-metal CMOS. An offset calibrating method is used to improve the performance of ADC. To reduce the input capacitance of the ADC and the amount of calibration circuit, the active interpolation technique is applied. Measured results show the ADC achieves a SNDR of 32.5 dB for a 7 MHz input at 1 GS/s, and 25.4 dB for a 108-MHz input. The power consumption is 550 mW at 1 GS/s from a 1.8-V supply.

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2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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