晶圆上无线测试的可行性研究

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI:10.1109/VDAT.2008.4542472

Piljae Park, C. Yue

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引用次数: 9

摘要

本文对晶圆无线测试的可行性进行了评估。用无线数据链路取代昂贵的高频探头卡，可以潜在地降低测试成本。晶圆级无线测试的关键元件包括片上天线和射频收发器。设计了一个24ghz的片上折叠偶极子天线，以适应硅芯片之间的刻痕线。测得天线增益为-22.6 dBi。给出了片上天线与高增益喇叭天线测试仪之间数据链路的功耗预算。我们的研究结果验证了无线测试所需的信噪比和天线带宽是可以实现的。根据测得的天线特性，给出了几个无线测试实例。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A feasibility study of on-wafer wireless testing

The feasibility of on-wafer wireless test is assessed in this paper. By replacing expensive high-frequency probe cards with wireless data link, testing cost can potentially be lowered. Key elements for wireless test at the wafer level include on-chip antenna and RF transceivers. A 24-GHz on-chip folded dipole antenna has been designed to fit in the scribe-lines between the silicon dies. The measured antenna gain shows -22.6 dBi. The power budget for a data link between a wafer with on-chip antenna and a tester equipped with high-gain horn antenna is presented. Our finding verifies that the required SNR and antenna bandwidth for wireless test can be achieved. Based on the measured antenna characteristics, several wireless test examples are illustrated.

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来源期刊

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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