用于组1 ~ 3mb - ofdm超宽带无线接收机的带分流峰值负载的CMOS低噪声放大器

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) Pub Date : 2008-04-23 DOI:10.1109/VDAT.2008.4542460

Zhe-Yang Huang, Che-Cheng Huang, Chun-Chieh Chen, C. Hung, C. Jou

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引用次数: 2

摘要

本文设计了一种用于超宽带无线接收系统的CMOS低噪声放大器(LNA)。该设计由宽带输入阻抗匹配网络、带并联峰值负载的两级级联码放大器和用于测量目的的输出缓冲器组成。采用umc0.18 μ m标准射频CMOS工艺制备。LNA在2.3G Hz-8.0 GH之间提供14.1 dB的最大功率增益，同时通过1.8 V电源消耗18.6 mW(包括缓冲器)。在3.1 GHz ~ 8.0 GHz频段内，最小噪声系数为2.0 dB。在整个带宽范围内，也实现了输入回波损耗低于-7.1 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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CMOS low-noise amplifier with shunt-peaking load for group 1∼3 MB-OFDM ultra-wideband wireless receiver

In this paper, a CMOS low-noise amplifier (LNA) is designed for ultra-wideband (UWB) wireless receiver system. The design consists of a wideband input impedance matching network, two stage cascode amplifiers with shunt-peaking load and an output buffer for measurement purpose. It was fabricated in UMC 0.18 mum standard RF CMOS process. The LNA provides 14.1 dB maximum power gain between 2.3G Hz-8.0 GH while consuming 18.6 mW (including buffer) through a 1.8 V supply. Over the 3.1 GHz-8.0 GHz frequency band, a minimum noise figure is 2.0 dB. The input return loss is lower than -7.1 dB in the entire bandwidth has also been achieved.

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来源期刊

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

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