Chueh-Hao Yu, Ching-Hsuan Hsieh, T. Shia, Wen-Tzao Chen
{"title":"A 90nm 10-bit 1GS/s current-steering DAC with 1-V supply voltage","authors":"Chueh-Hao Yu, Ching-Hsuan Hsieh, T. Shia, Wen-Tzao Chen","doi":"10.1109/VDAT.2008.4542461","DOIUrl":null,"url":null,"abstract":"This paper discusses the design of a 90 nm CMOS IV 10-bit lGS/s current-steering D/A converter. The proposed design operates under low supply voltage of IV and gives a large differential full- scale output of 0.5 Vppd. A wide full-scale current range of 2-10 mA is designed and the output impedance of the DAC is optimized for different full-scale currents by a bias circuit related to them. The post-layout simulation results show that the SFDR and ENOB are 50.64 dBc and 7.86 bit respectively with a full-scale 308.59 MHz input at lGS/s and more than 50 dB and 8 bit respectively when the signal bandwidth is less than 200 MHz. The converter consumes a total power of 23 mW at 1 V supply. It is designed for 90 nm CMOS technology and has an active area of 0.47 mm2.","PeriodicalId":156790,"journal":{"name":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2008.4542461","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper discusses the design of a 90 nm CMOS IV 10-bit lGS/s current-steering D/A converter. The proposed design operates under low supply voltage of IV and gives a large differential full- scale output of 0.5 Vppd. A wide full-scale current range of 2-10 mA is designed and the output impedance of the DAC is optimized for different full-scale currents by a bias circuit related to them. The post-layout simulation results show that the SFDR and ENOB are 50.64 dBc and 7.86 bit respectively with a full-scale 308.59 MHz input at lGS/s and more than 50 dB and 8 bit respectively when the signal bandwidth is less than 200 MHz. The converter consumes a total power of 23 mW at 1 V supply. It is designed for 90 nm CMOS technology and has an active area of 0.47 mm2.